Senior FPGA Verification Engineer (SystemVerilog/UVM)
$98.7k - $157.9kTeradyne Inc
A leading technology company is seeking a Digital Logic Verification Engineer at their North Reading, MA development center. The ideal candidate has over 3 years of experience in digital logic verification, with strong skills in System Verilog and UVM. Responsibilities include reviewing design requirements, developing testbench architecture, and collaborating with logic designers. The position offers a competitive salary between $98,700 and $157,900, along with robust health and well-being benefits. This role is not eligible for visa sponsorship. #J-18808-Ljbffr Teradyne
Vacancy posted 4 days ago
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