Exciting Opportunity for PCIe Silicon Validation & Debug Engineer_ Sunnyvale, CA (Onsite)

Role: PCIe Silicon Validation & Debug Engineer

Location: Sunnyvale CA (Onsite)

Duration: 9+ Months Contract

Job Description:

Summary

We are seeking a skilled PCIe Engineer to join our Silicon Engineering team. The ideal candidate will have deep expertise in PCI Express (PCIe) interfaces and protocols, with hands-on experience in test development, analysis, and debug across both pre-silicon and post-silicon environments. You will play a critical role in ensuring the functional correctness, performance, and compliance of PCIe IP and SoC-level interconnects.

Key Responsibilities

Pre-Silicon

• Develop and execute test plans for PCIe Gen3/Gen4/Gen5/Gen6 IP blocks and SoC-level integration
• Create directed and constrained-random tests targeting PCIe Transaction Layer (TLP), Data Link Layer (DLLP), and Physical Layer (PHY) functionality
• Perform protocol-level analysis using VIP (Verification IP) environments and bus functional models
• Debug RTL-level issues related to link training, power management (ASPM, L-states), equalization, and error handling
• Collaborate with design teams on coverage closure, assertions, and functional coverage models

Post-Silicon

• Bring up and validate PCIe links on silicon platforms (FPGA, emulation, and first silicon)
• Develop and execute post-silicon validation test plans covering link training, enumeration, data integrity, error injection, and compliance
• Debug silicon-level issues using protocol analyzers (e.g., Keysight, Teledyne LeCroy), oscilloscopes, and logic analyzers
• Perform root-cause analysis of PCIe link failures, packet errors, and performance degradation
• Characterize PCIe PHY performance including jitter, eye diagrams, and signal integrity
• Collaborate with platform, firmware, and BIOS teams to resolve system-level PCIe issues
• Drive compliance and interoperability testing per PCI-SIG specifications

General

• Analyze PCIe specification updates and assess impact on existing IP/SOC designs
• Automate test infrastructure, result parsing, and regression frameworks
• Document findings, debug methodologies, and test coverage metrics
• Contribute to team knowledge sharing

Required Qualifications

• Education: B.S./M.S./Ph.D. in Electrical Engineering, Computer Engineering, or related field
• Experience: 3 8+ years of experience in PCIe validation, verification, or silicon bring-up
• Strong understanding of PCIe specification (Gen3 through Gen5/Gen6), including:
• Transaction Layer: TLP types, ordering rules, flow control, completion handling
• Data Link Layer: ACK/NAK, replay, LCRC, DLLP
• Physical Layer: Link training (LTSSM), equalization, encoding (8b/10b, 128b/130b)
• Power management: ASPM, L-states, D-states
• Proficiency in System Verilog/UVM for pre-silicon test development
• Experience with protocol analyzers and lab debug tools for post-silicon validation
• Familiarity with scripting languages (Python, Perl, Tcl) for test automation and log parsing
• Solid understanding of PCIe enumeration, BAR programming, and configuration space
• Experience with FPGA prototyping or emulation platforms is a plus

Preferred Qualifications

• Experience with CXL (Compute Express Link) or other PCIe-based protocols
• Knowledge of signal integrity concepts (S-parameters, eye diagrams, jitter analysis)
• Familiarity with compliance testing per PCI-SIG specifications and test suites
• Experience with NVMe, CCIX, or UCIe protocols
• Background in SoC-level integration and system-level validation
• Understanding of BIOS/firmware interactions with PCIe subsystems

Contributions to PCIe IP development or architecture definition.

Best Regards,

Biplab Deb

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