SOC Physical Design Static Timing Analysis Engineer

As a Physical Design Timing Engineer, you will play a pivotal role in shaping the performance, power efficiency, and functionality of Intel’s cutting‑edge System‑on‑Chip (SoC) designs. Your expertise will directly impact product quality, enabling groundbreaking advancements in technology that drive computing innovation. You will collaborate across multiple teams, contributing to the creation and optimization of high‑performance, low‑power solutions while developing methodologies that enhance efficiency and operational excellence. This is an exciting opportunity to work on complex designs that have a global impact, delivering solutions that power today’s world and inspire tomorrow’s possibilities. Key Responsibilities Perform SOC level timing analysis and optimization, ensuring designs meet functional and performance requirements. Generate and verify timing constraints while addressing timing violations at the chip or block level for SoCs. Conduct timing rollups and develop optimized clock networks for functionality, performance, and power efficiency. Define methodologies to produce high‑quality timing models and enable efficient physical design execution. Establish appropriate process, voltage, and temperature (PVT) conditions for timing analysis, aligning with product plans and binning strategies. Work closely with the clocking team and full‑chip designers to balance timing fixes, power delivery, clocking, and partitioning. Collaborate with architecture, clocking design, DFT, and logic design teams to develop flows for chip integration and validate clock network performance guidelines. Contribute to the development of tools, flows, and methodologies that enhance SoC physical design and timing processes. Qualifications Minimum Qualifications: Bachelor’s degree with 8+ years, master’s degree with 6+ years, or PhD with 4+ years in Electrical Engineering, Computer Engineering, Computer Science, or a related field. 7+ years technical proficiency in SOC level static timing analysis, clock network design, and timing closure methodologies. 3+ years of experience with the following skills: strong expertise in timing constraint adaptation, physical design knowledge, and optimization techniques; proficiency with industry‑standard tools for timing analysis, extraction, and physical design; familiarity with TCL scripting and timing budgeting processes. Preferred Skills/Experience: Demonstrated ability to collaborate across diverse teams and drive innovative solutions for SoC designs; experience with SoC clocking methodologies, disciplined execution, and problem‑solving in digital design; knowledge of tools, flows, and methodologies for high‑performance physical design; strong communication skills and ability to articulate technical concepts effectively; DFT architecture knowledge is a strong plus. Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, Arizona, Phoenix Additional Locations: US, California, Santa Clara Business group: The Central Engineering Group (CEG) is Intel’s data‑driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC, and Foundry Enablement. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Annual Salary Range for jobs which could be performed in the US: $164,470.00‑311,890.00 USD. The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job‑related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this Role: This role will be eligible for our hybrid work model which allows employees to split their time between working on‑site at their assigned Intel site and off‑site. Benefits: We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. #J-18808-Ljbffr