Mask Layout Designer

Choose a partner with intimate knowledge of your industry and first-hand experience of defining its future.Your locationYour locationIndustriesChoose a partner with intimate knowledge of your industry and first-hand experience of defining its future.# Analog Layout EngineerSan Francisco, Santa ClaraChoosing Capgemini means choosing a company where you will be empowered to shape your career in the way you’d like, where you’ll be supported and inspired by a collaborative community of colleagues around the world, and where you’ll be able to reimagine what’s possible. Join us and help the world’s leading organizations unlock the value of technology and build a more sustainable, more inclusive world.The base compensation range for this role in the posted location is: $97,700 to $ 203,800 per year.Capgemini provides compensation range information in accordance with applicable national, state, provincial, and local pay transparency laws. The base compensation range listed for this position reflects the minimum and maximum target compensation Capgemini, in good faith, believes it may pay for the role at the time of this posting. This range may be subject to change as permitted by law.The actual compensation offered to any candidate may fall outside of the posted range and will be determined based on multiple factors legally permitted in the applicable jurisdiction.These may include, but are not limited to: Geographic location, Education and qualifications, Certifications and licenses, Relevant experience and skills, Seniority and performance, Market and business consideration, Internal pay equity.It is not typical for candidates to be hired at or near the top of the posted compensation range.In addition to base salary, this role may be eligible for additional compensation such as variable incentives, bonuses, or commissions, depending on the position and applicable laws.**Capgemini offers a comprehensive, non-negotiable benefits package to all regular, full-time employees.** In the U.S. and Canada, available benefits are determined by local policy and eligibility and may include: * Paid time off based on employee grade (A-F), defined by policy: Vacation: 12-25 days, depending on grade, Company paid holidays, Personal Days, Sick Leave* Medical, dental, and vision coverage (or provincial healthcare coordination in Canada)* Retirement savings plans (e.g., 401(k) in the U.S., RRSP in Canada)* Life and disability insurance* Employee assistance programs* Other benefits as provided by local policy and eligibility**Important Notice:** Compensation (including bonuses, commissions, or other forms of incentive pay) is not considered earned, vested, or payable until it becomes due under the terms of applicable plans or agreements and is subject to Capgemini’s discretion, consistent with applicable laws. The Company reserves the right to amend or withdraw compensation programs at any time, within the limits of applicable legislation.**Disclaimers**Capgemini is an Equal Opportunity Employer encouraging inclusion in the workplace. Capgemini also participates in the Partnership Accreditation in Indigenous Relations (PAIR) program which supports meaningful engagement with Indigenous communities across Canada by promoting fairness, accessibility, inclusion and respect. We value the rich cultural heritage and contributions of Indigenous Peoples and actively work to create a welcoming and respectful environment. All qualified applicants will receive consideration for employment without regard to race, national origin, gender identity/expression, age, religion, disability, sexual orientation, genetics, veteran status, marital status or any other characteristic protected by law.This is a general description of the Duties, Responsibilities and Qualifications required for this position. Physical, mental, sensory or environmental demands may be referenced in an attempt to communicate the manner in which this position traditionally is performed. Whenever necessary to provide individuals with disabilities an equal employment opportunity, Capgemini will consider reasonable accommodations that might involve varying job requirements and/or changing the way this job is performed, provided that such accommodation does not pose an undue hardship. Capgemini is committed to providing reasonable accommodation during our recruitment process. If you need assistance or accommodation, please reach out to your recruiting contact.Please be aware that Capgemini may capture your image (video or screenshot) during the interview process and that image may be used for verification, including during the hiring and onboarding process.Click the following link for more information on your rights as an Applicant in the United States. Capgemini is a global business and technology transformation partner, helping organizations to accelerate their dual transition to a digital and sustainable world, while creating tangible impact for enterprises and society. It is a responsible and diverse group of 340,000 team members in more than 50 countries. With its strong over 55-year heritage, Capgemini is trusted by its clients to unlock the value of technology to address the entire breadth of their business needs. It delivers end-to-end services and solutions leveraging strengths from strategy and design to engineering, all fueled by its market leading capabilities in AI, generative AI, cloud and data, combined with its deep industry expertise and partner ecosystem.## About the job you are consideringWe are seeking an experienced Analog / RF Layout Designer to provide onsite support for advanced semiconductor nodes while partnering with a highly collaborative, global design and layout organization. In this role, you will contribute to cutting-edge analog and mixed-signal IP development, working across complex technologies such as FinFET and deep sub-micron processes. This is an excellent opportunity for a hands-on layout expert who thrives in technically challenging environments and enjoys end-to-end ownership from block-level design through top-level integration.## Your role* Independently develop **block‐level and IP‐level analog/RF layouts**, partnering closely with circuit designers and global layout teams to drive designs from concept to tape‐out.* Own **floorplanning, placement, routing, and optimization** for complex analog and mixed‐signal blocks, including **SerDes, ADC/DACs, PLLs, and related IPs**.* Lead and support **top‐level integration** of multiple analog and mixed‐signal blocks within larger SoCs.* Apply deep expertise in **advanced deep sub‐micron and FinFET process technologies**, incorporating fabrication, EM, ESD, latch‐up, and reliability considerations into layouts.* Resolve complex **DRC, LVS, antenna, and verification issues**, exercising strong technical judgment while collaborating across geographies and mentoring or guiding team members as a technical lead.## Your skills and experience* Bachelor’s degree in Electrical Engineering, Electronics, or a related field.* 6+ years of hands-on experience in analog and/or RF layout design (8+ years preferred).* Proven experience with analog floor planning and layout for complex modules such as SerDes, ADC/DAC, PLLs, and similar high-speed or precision circuits.* Strong understanding of analog layout best practices for deep sub-micron CMOS and FinFET technologies. #J-18808-Ljbffr