Senior Principal Engineer -Hardware Signal Integrity & Power Integrity

Job Description

Job Description

Job Title: Senior Principal Engineer, Hardware Application Engineering — Signal Integrity & Power Integrity

Location: Santa Clara, CA, US (Onsite – 5 days/week)

Department: Engineering / Architecture | Customer Solutions Group

Position Type: Full-time (New Position)

Salary Range: $199,800 – $266,400 / year (No variable compensation/bonus flexibility)

Relocation: Eligible

Visa Sponsorship: Available

As the Senior Principal Engineer for Signal Integrity (SI) and Power Integrity (PI) , you will serve as the senior technical authority responsible for ensuring that customer platforms built on our Ethernet Switch and UALink silicon meet the highest performance and quality thresholds — from first prototype through mass-production deployment.

This is a deep individual contributor role with high customer and ODM visibility. Your mission is to implement best-in-class SI and PI practices across every platform you touch, ensuring performance across hundreds of thousands of units in real-world deployments. You will own layout guideline definitions, post-silicon channel extraction and simulation, compliance testing, and SerDes tuning guidance, while playing a key technical role in our evolution toward 224G and 448G SerDes-class systems and emerging open AI fabric standards.

• Technical Authority: Serve as the senior SI/PI technical lead for customer platforms utilizing our Ethernet switches and UALink silicon from early channel definition through mass-production qualification.
• Layout & Routing Guidelines: Define, maintain, and drive adoption of layout/routing guidelines for high-speed SerDes channels, power delivery networks (PDN), and sensitive analog interfaces.
• Extraction & Simulation: Perform post-silicon channel extraction, full-channel simulation, and "what-if" analyses; recommend targeted layout and stack-up fixes to achieve best-in-class margins.
• Power Integrity (PI) Optimization: Run/review PDN simulations covering impedance, IR drop, decoupling effectiveness, transient response, and droop for high-current ASICs.
• Compliance & Lab Debug: Lead lab characterization and compliance testing (BER/SER, eye-opening margins, jitter, return loss, crosstalk) using VNAs, BERTs, scopes, TDR, and jitter analyzers.
• SerDes Tuning: Provide tuning guidance to customers using simulation data, lab measurements, and field telemetry; collaborate with silicon teams to refine methodologies.

• ODM Engagement: Work directly with ODMs on SI/PI guidance, board design reviews, and qualification activities.
• Reference Designs: Support the definition and validation of reference designs for new silicon, owning SI/PI from channel budgeting to customer release.
• Feedback Loops: Translate customer power/performance constraints into structured feedback for internal silicon, packaging, and platform engineering teams.
• Training & Mentorship: Develop and deliver technical SI/PI training to internal teams, ODMs, and customers on high-speed design best practices and debug techniques.
• Strategic Roadmap Input: Contribute to next-generation product definitions (112G, 224G, and 448G PAM4 systems) by bringing real-world field insights into architecture discussions.

• Raise the Bar: Ensure customer designs are not just compliant, but production-robust at scale.
• Bridge Engineering Teams: Act as the technical nexus between customers, ODMs, internal silicon teams, and hardware engineering.
• Technical Ambassadorship: Represent our SI/PI engineering expertise in executive briefings, strategic customer meetings, and industry forums.
• Travel: Project-driven travel to customer sites, ODMs, and testing labs as needed.

• Education: PhD, Master’s, or Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related technical field.
• Overall Experience: 15+ years in hardware design, development, and validation of high-speed networking or compute systems.
• Domain Focus: 10+ years of dedicated experience in Signal Integrity (SI) and Power Integrity (PI) on high-speed SerDes platforms (25G NRZ through 112G/224G PAM4).
• Full SI/PI Lifecycle Expertise: Proven track record in channel modeling/budgeting, stack-up guidelines, post-layout extraction, design-fix recommendations, and PDN simulations (IR drop, transient response, decoupling).
• EDA Toolchains: High proficiency in leading EDA tools (e.g., Ansys HFSS/SIwave, Cadence Sigrity/Clarity/PowerSI, or equivalent).
• Lab Debug Skills: Hands-on mastery of VNAs, BERTs, real-time/sampling oscilloscopes, TDRs, jitter analyzers, and compliance kits.
• Customer Facing: Demonstrated experience managing complex customer/ODM engagements and resolving critical deployment issues.
• Communication: Exceptional ability to articulate technical concepts and influence senior engineering stakeholders across global teams.

• Direct experience with Ethernet switch platforms or emerging open AI fabric architectures .
• Background in reference platform SI/PI definition and customer enablement for silicon solutions.
• Experience supporting SI/PI for platforms deployed in megascale data centers at volume.
• Familiarity with ODM/CM manufacturing flows, DFM/DFT, reliability testing, and high-volume variability.
• Familiarity with chip-to-module, copper cable, and connector ecosystems for high-speed channels.

Note on Experience Level: While 15+ years represents the standard benchmark, exceptionally talented candidates with fewer years of experience who demonstrate technical mastery through high-impact project work or industry recognition are strongly encouraged to apply.