Principal Mixed-Signal Engineer

Job Description Insight Global is looking for a Principal Mixed‑Signal Engineer that will be working on site in Austin, TX and support a public‑private partnership of preeminent semiconductor systems and defense electronics companies, national labs, and academic institutions. Their mission is to advance the state‑of‑the‑art in critical semiconductor domains such as advanced packaging, and in the process to help restore U.S. leadership in semiconductor manufacturing. They are developing cutting‑edge semiconductor manufacturing equipment and processes that will define future roadmaps of semiconductor logic, memory, heterogenous integration, chip cooling, etc. They are backed by $1.4 billion in combined funding from DARPA, Texas state initiatives, and strategic partners, they are building foundational capabilities in advanced packaging and integrated design infrastructure to restore U.S. leadership in microelectronics manufacturing. Responsibilities Design and develop high‑speed mixed‑signal I/O circuits for UCIe 2.5D and 3.0D die‑to‑die interfaces in 2.5D/3D microsystems—enabling robust, low‑latency chiplet interconnect across AI, HPC, and defense platforms. Architect and optimize SerDes, clock/data recovery (CDR), equalization, and transceiver circuits for high‑speed die‑to‑die and chip‑to‑chip links, including UCIe, PCIe physical layers. Collaborate with packaging, EDA, and system modeling teams to co‑optimize mixed‑signal I/O performance across heterogeneous integration stacks—accounting for signal integrity, power delivery, crosstalk, and thermal effects unique to 3DHI. Lead silicon bring‑up, bench characterization, and production testing of high‑speed I/O and mixed‑signal circuits—developing test methodologies, ATE programs, and yield‑improvement strategies from prototype through volume production. Engage with industry partners and standards bodies (UCIe Consortium) to influence specification development and ensure their physical‑layer implementations remain standards‑aligned. Mentor internal design teams on mixed‑signal design methodologies, high‑speed measurement techniques, and production test best practices for multi‑die systems. Translate mixed‑signal design innovations into IP roadmaps and reference designs, driving alignment between research, productization, and customer enablement for UCIe‑based chiplet ecosystems. Skills and Requirements Ph.D. or M.S. in Electrical Engineering with emphasis on analog/mixed‑signal or high‑speed circuit design (or equivalent practical experience). 12+ years of experience in mixed‑signal or high‑speed I/O circuit design for SoC/ASIC, with direct involvement in SerDes, UCIe, or comparable die‑to‑die/chip‑to‑chip interface IP. Deep expertise in high‑speed transceiver design—including TX/RX front‑ends, CDR, equalization (CTLE, DFE), PLLs/DLLs, and signal integrity analysis for multi‑Gbps links. Hands‑on experience with silicon bring‑up, lab characterization (high‑speed oscilloscopes, BER testers, network analyzers), and production test development on ATE platforms. Proficiency with industry‑standard analog/mixed‑signal EDA tools (Cadence Virtuoso/Spectre, Synopsys HSPICE, Ansys HFSS/SIwave) and parasitic‑aware simulation methodologies. Strong cross‑disciplinary collaboration—able to interface with digital design, packaging, EDA, and process engineering teams to close mixed‑signal performance across the 3DHI stack. Proven record of taking high‑speed mixed‑signal IP from design through silicon validation and into production. Direct design experience with UCIe 2.5D (single‑ended, shoreline‑optimized) and/or UCIe 3.0D (hybrid‑bonding, ultra‑short‑reach) physical‑layer implementations. Familiarity with heterogeneous (multi‑material and/or multi‑function) integration challenges—including crosstalk modeling, power delivery network design, and signal integrity in 2.5D/3D hybrid‑bonding and interposer stacks. Experience designing SerDes or high‑speed I/O IP at 28 Gbps and above (e.g., 56G/112G PAM4), with end‑to‑end ownership spanning specification, design, tape‑out, silicon characterization, and production test. Knowledge of interconnect and chiplet standards (UCIe, BoW, CXL, PCIe Gen 5/6, NVLink, UALink) and their physical‑layer requirements and compliance testing. Track record of publications, patents, or industry leadership in mixed‑signal circuit design, high‑speed I/O, or SerDes architectures. We are a company committed to creating diverse and inclusive environments where people can bring their full, authentic selves to work every day. We are an equal opportunity/affirmative action employer that believes everyone matters. Qualified candidates will receive consideration for employment regardless of their race, color, ethnicity, religion, sex (including pregnancy), sexual orientation, gender identity and expression, marital status, national origin, ancestry, genetic factors, age, disability, protected veteran status, military or uniformed service member status, or any other status or characteristic protected by applicable laws, regulations, and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application or recruiting process, please send a request to View email address on click.appcast.io. To learn more about how we collect, keep, and process your private information, please review Insight Global's Workforce Privacy Policy: #J-18808-Ljbffr Insight Global