Lead Verification Architect for Cache-Coherent Interconnects
SiFive
SiFive is seeking a Senior Staff Design Verification Engineer to lead the verification of high-performance cache-coherent interconnects. In this critical role, you will develop verification strategies, identify risks early, and work collaboratively with various teams to ensure protocol correctness and subsystem integration. Ideal candidates will have a strong background in ASIC or SoC verification, with an emphasis on SystemVerilog and cache-coherent systems. This position requires excellent communication skills and a dedication to quality in a fast-paced environment. #J-18808-Ljbffr
Vacancy posted 3 days ago
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