Principal ASIC DFT Design Engineer - Terawave
$269.18k - $376.84kBlue Origin
Application close date: Applications will be accepted on an ongoing basis until the requisition is closed. At Blue Origin, we envision millions of people living and working in space for the benefit of Earth. We’re working to develop reusable, safe, and low-cost space vehicles and systems within a culture of safety, collaboration, and inclusion. Join our team of problem solvers as we add new chapters to the history of spaceflight! Blue Origin is pioneering the future of space-based connectivity with TeraWave, a revolutionary satellite communications network designed to deliver symmetrical data speeds of up to 6 Tbps anywhere on Earth. This network will service tens of thousands of enterprise, data center, and government users who require reliable connectivity for critical operations. As a Principal ASIC DFT Designer on the ASIC Engineering SOC Team, you will own design for test architecture for the TeraWave System on Chip (SOC) program. You will define the test strategy for large multi-block SOC designs, implement scan, compression, and built in self test infrastructure, and deliver the test vectors that qualify silicon on automated test equipment. This is a senior individual contributor role with technical leadership scope and no direct reports. Your work spans specification through silicon bring up, including ATE pattern debug and support for defect and yield analysis, and it directly determines test quality and manufacturability for the program. Responsibilities:
- Define DFT architecture and test strategy for large multi-block SOC designs
- Author DFT specifications covering scan, compression, boundary scan, and test access mechanisms
- Implement scan chain insertion, test clock control, and on chip compression logic
- Design memory and logic built in self test infrastructure for embedded memories and logic
- Generate and validate DFT vectors for silicon bring up and production test programs
- Debug ATE pattern failures and drive resolution with design and product engineering teams
- Support defect analysis and yield improvement using test coverage and silicon failure data
- Review test coverage and DFT timing metrics with physical design and verification teams
- Bachelor's degree in Electrical Engineering, Computer Engineering, or related technical field
- Minimum 10 years of experience in design for test for complex digital SOCs
- Experience defining DFT architecture and specifications for large multi-block SOC designs
- Experience with DC and AC scan design and memory built in self test implementation
- Experience generating ATPG patterns for automated test equipment and debugging ATE patterns
- Master's degree in Electrical Engineering, Computer Engineering, or related technical field
- Experience with logic built in self test implementation and signature based test methodologies
- Experience with defect analysis and yield improvement for advanced process node silicon
- Experience with hierarchical DFT and IEEE 1500 or IEEE 1687 test access standards
- Experience with commercial DFT tool flows such as Tessent, DFTMAX, or Modus
- Experience with test time and test cost reduction through pattern and compression optimization
- Strong written and verbal communication skills for presenting test strategy to technical stakeholders
- Required for all positions: Blue’s Standard Background Check
- Required for Certain Job Profiles: Defense Biometric Identification System (DBIDS) background check if at any time the role requires one to be on a military installation
- Required for Certain Job Profiles: Drivers who operate Commercial Motor Vehicles with a Gross Vehicle Weight (GVW), Gross Vehicle Weight Rating (GVWR) or combination of power unit and trailer that meets or exceeds 10,001 lbs. and/or transports placardable amounts of hazardous materials by ground in any vehicle on a public road while in commerce, may be subject to additional Federal Motor Carrier Safety Regulations including: Driver Qualification Files, Medical Certification (obtained before onboarding), Road Test, Hours of Service, Drug and Alcohol Testing, vehicle inspection requirements, CDL requirements (if applicable) and hazardous materials transportation/shipping training.
- Required for certain Job Profiles: Ability to obtain and maintain Merchant Mariner Credential, which includes pre-employment and random drug testing as well as DOT physical
- Benefits include: Medical, dental, vision, basic and supplemental life insurance, paid parental leave, short and long-term disability, 401(k) with a company match of up to 5%, and an Education Support Program.
- Stock Options for all regular employees (working at least 20 hours/week)
- Paid Time Off: Up to four (4) weeks per year based on weekly scheduled hours, and up to 14 company-paid holidays.
- Dependent on role type and job level, employees may be eligible for benefits and bonuses based on the company's intent to reward individual contributions and enable them to share in the company's results, or other factors at the company's sole discretion. Bonus amounts and eligibility are not guaranteed and subject to change and cancellation. Please check with your recruiter for more details.
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