Design Verification Engineer

Job-ID16513851Reference21-03603 Testbench development - System Verilog UVM and C tests Integration/development of C tests/APIs and SW build flow Integration/development of UVM mailboxes and HW/SW communication components Integration of lower level UVM testbenches Test plan development Power Aware testbench development and simulations Seamless porting between simulation/emulation/prototyping platforms Regression setup and debug for RTL/Gate Level Netlist/UPF PA sim/Emulation/Proto Coverage collection and closure Working with cross functional teams (DV/Arch/Design/FW) to identify coverage scope Minimum Qualifications: 2-3 year of experience in RTL Design and Verification area of which 2+ years of experience in SoC Design Verification and HW/SW verification or o Master Degree in relevant subject and 1 year of internship and/or verification or design specific projects Knowledge of System Verilog UVM and vertical testbench integration Knowledge of low level HW/SW interaction and debug Basic Knowledge of multi CPU and debug architectures Some Experience with development of fully automated flows Preferred Qualification:

• Experience with low level SW debug - disasm, Tarmac, trace
• Experience with RISC-V architecture

Experience with coresight architecture Experience with embedded SW low level concepts and debug - Tarmac, ROM, RAM, linkers, elf, disasm, code sections, cache, security Experience with coverage merging across simulation and emulation Experience with Power Aware and Gate Level Netlist in Emulation Experience with development of fully automated flows Experience with Gate Level Simulations • Python Scripting Additional Job Details: 1 - C Programming Language (P3 - Advanced) | 2 - C++ Programming Language (P3 - Advanced) | 3 - PERL Scripting (P3 - Advanced) Primary Skill Python