AI Lead Project Manager

Kforce's client in Boston, MA is seeking an AI Lead Project Manager for Electric Operations Technology. This is a senior role responsible for the end-to-end delivery of a substation Edge AI product. This position is the functional equivalent of the former Engineering Lead - combining deep technical authority with program ownership to drive a complex, multi-partner integration program from development through field deployment. The successful candidate owns the full technical integration stack: embedded hardware, software, DSP algorithms, AI/ML engine and models, and OT-grade cybersecurity. The AI Lead Project Manager will serve as the primary technical interface between internal stakeholders and external partners, and as the accountable delivery lead for integration testing and operational deployment across substation sites.

• To be considered for this position, candidates must have experience in a similar role, or they must possess significant knowledge, experience, and abilities to successfully perform the responsibilities listed
• Relevant education and/or training will be considered a plus

• Power systems/substation OT: Protection and control systems, IEDs, SCADA, substation automation (IEC 61850, DNP3, Modbus)
• Embedded systems integration: Real-time OS, edge compute platforms, hardware bring-up, BSPs, driver-level software
• DSP/signal processing: Familiarity with power system signal processing concepts (phasor estimation, FFT, event detection) as applied to protection or power quality
• AI/ML at the edge: Understanding of inference pipeline deployment - model optimization (quantization, pruning), inference runtimes (ONNX, TensorRT, TFLite), and model performance validation
• OT Cybersecurity: Practical knowledge of IEC 62443 and NERC CIP standards; secure hardware and software architecture in critical infrastructure environments
• Systems engineering: Requirements management, interface control, verification and validation (V&V), configuration management
• Integration testing: Experience authoring and executing integration master test plans across HW/SW stacks; HIL test environments