Senior Technologist, Hardware Development Engineering - (Roseville)

Company DescriptionWD is building the infrastructure behind the AI-driven data economy.As AI scales, so does data. Every interaction, every model, every system generates data that must be stored, managed, and made accessible over time. That’s where we come in.We combine deep engineering expertise with global-scale manufacturing to deliver the storage systems that make AI possible, powering hyperscale data centers, cloud platforms, and enterprise infrastructure worldwide.This isn’t theoretical work. It’s real systems, at real scale, people solving some of the hardest challenges in technology today.We’re looking for people who want to build, solve, and operate at that level.Join us and let’s shape the future of data.Job DescriptionWe are seeking an Expert-level Hardware Engineer who is equally strong in board-level hardware design and ASIC interface / integration (I/O, package, power integrity, DFT/test, analog, and signal integrity). This is a hands-on role for a recognized subject matter expertise in delivering complex hardware from concept through production, including deep lab bring-up and root-cause complex issues, able to debug across silicon, package, and board.QualificationsREQUIREDProfessional hardware engineering experience.Proven ownership of multiple complex programs through the full lifecycle: architecture design build bring-up debug qualification production ramp sustaining.Demonstrated, hands-on experience spanning both:Board/system hardware design (schematic ownership, layout partnership, bring-up, debug, standards compliance, manufacturing support)ASIC I/O and integration (I/O architecture decisions, package/substrate considerations, PI/SI co-design, tape-out support, DFT/test hooks)Cutting-Edge High-Speed Interfaces Hands-on experience integrating and debugging leading-edge Ethernet and PCIe interfaces, including:100G/200G Ethernet PAM4 transceivers (system/channel design, equalization concepts, BER/PRBS testing, standards compliance planning and test)PCIe Gen 6 (system/channel design, equalization concepts, BER/PRBS testing, standards compliance planning and test)Demonstrated ability to design and simulate high-speed links across die/ASIC package/PCB/connectors/cabling, balancing SI/PI/EMI and manufacturing constraints.FPGA Board Design Proven experience designing complex boards using cutting-edge FPGAs (e.g., high-end families with high-speed transceivers), including:Power architecture and sequencing for FPGA multi-rail systemsHigh-speed transceiver channel design, with associated reference clock design,reset/boot/strapBring-up and debug using vendor tools, link training, PRBS/IBERT-style testing, and lab correlationOwnership of FPGA-based platform bring-up from first power-on through high-speed link validation and system integration.AMD FPGA Knowledge preferredBoard-Level Design Expert schematic design and review for high-complexity boards (compute/networking/accelerator-class or equivalent).Strong experience with:Multi-rail power distribution networks (frequency domain impedance control, sequencing, fault handling)High-speed interfaces (DDR, PCIe, Ethernet/SerDes-based links, USB, I2C, SPI, MIPI—based on product needs)Controlled impedance trace design (understanding manufacturing and cost tradeoffs)Clocking/reset/fault tolerant architectures and debug access designGeneral analog circuit designProven partnership with layout teams to define and enforce:Stackups, reference planes, return paths, via design and strategy, routing constraintsDifferential pair controlled impedance routing, channel constraints, connector strategy, manufacturabilitySignal Integrity (SI) & Power Integrity (PI) Across Die / Package / BoardSI design experience: Insertion loss, return loss, eye/jitter concepts, electrical noise abatement, termination, discontinuities, correlation of models to measurements.Deep PI/PDN experience: target impedance approach, decap strategy, anti-resonance mitigation, transient response, measurement and correlation.Practical EMI/EMC grounding/shielding/filtering understanding grounded in design and lab realities.ASIC I/O, Package, and Power Co-DesignAbility to own or co-own ASIC I/O choices:I/O standards, voltage domains, ESD strategy, drive/slew tuning, noise coupling/SSO considerationsStrong understanding of package/substrate impacts:Pinout/ballout tradeoffs, escape routing constraints, lane swapping realitiesPackage parasitics effects on SI/PI and timing marginsThermal/mechanical considerations influencing reliability and assemblyPower architecture competence spanning system and ASIC-aware constraints (noise isolation, domain partitioning, bring-up hooks).DFT / Test Strategy Bridging Silicon Board ManufacturingStrong working knowledge of DFT concepts and productization:JTAG/boundary scan, scan/ATPG fundamentals, BIST/loopbacks/PRBS, on-chip monitors/telemetryExperience defining debug and manufacturing test strategy:Test access, test point strategy, coverage vs SI impact, failure analysis workflowsAnalog & Mixed-Signal Practical DepthPractical capability to own/review analog subsystems relevant to high-performance designs:Clock generation/distribution and jitter sensitivityFiltering/biasing, stability fundamentals, measurement integrity/noise couplingMixed-signal partitioning and grounding strategyHands-On Lab Debug ExpectationsExpert in structured bring-up and root-cause debug:Creation and execution of EVT test planHigh-speed measurement competence (Oscilloscopes, BERT, network analyzers, spectrum analyzers, probing strategy, fixtures, de-embedding awareness)Ability to correlate bench measurements back to simulation and drive corrective actionsTools & WorkflowFamiliarity with mainstream schematic/layout environments (e.g., Cadence/Altium/Mentor-class tools) and constraint-driven design practices.Comfortable with SI/PI modeling workflows (IBIS/AMI, S-parameters, SPICE-level reasoning) and validation against lab data.Strong documentation, design review, ECO, and risk-management disciplineOperates as a cross-functional technical leader across silicon, package, board, validation, test, manufacturing.Writes clear specs/constraints that prevent rework (I/O requirements, channel budgets, PDN targets, bring-up/test access).Drives design reviews that identify real risks early and mentors engineers across experience levels.Drive partnerships with key IP, component and manufacturers. Examples where you personally identified high-speed margin failures (examples: 100/200G PAM4 and/or PCIe Gen 6 or slower data rates) through SI/PI analysis or lab testing.Examples of cross-boundary root cause (ASIC package board) with measurable corrective actions.Examples where you improved observability/DFT/test hooks to accelerate bring-up and production readiness.PREFERREDAdvanced packaging or multi-die systems (e.g., chiplets/interposers/HBM-class integration).Ownership of qualification/compliance (EMC, safety, thermal/mechanical) and production yield improvement.Experience with design for low cost, second-source strategies, and sustained field reliability initiatives.Salary Range176,600.00-235,400.00Additional InformationWD is committed to providing equal opportunities to all applicants and employees and will not discriminate against any applicant or employee based on their race, color, ancestry, religion (including religious dress and grooming standards), sex (including pregnancy, childbirth or related medical conditions, breastfeeding or related medical conditions), gender (including a person’s gender identity, gender expression, and gender-related appearance and behavior, whether or not stereotypically associated with the person’s assigned sex at birth), age, national origin, sexual orientation, medical condition, marital status (including domestic partnership status), physical disability, mental disability, medical condition, genetic information, protected medical and family care leave, Civil Air Patrol status, military and veteran status, or other legally protected characteristics. We also prohibit harassment of any individual on any of the characteristics listed above. Our non-discrimination policy applies to all aspects of employment. We comply with the laws and regulations set forth in the Know Your Rights: Workplace Discrimination is Illegal” poster. Our pay transparency policy is available here.WD thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution.WD is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at View email address on apply.placed-app.com to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying.Based on our experience, we anticipate that the application deadline will be 08/13/2026(3 months from posting), although we reserve the right to close the application process sooner if we hire an applicant for this position before the application deadline. If we are not able to hire someone from this role before the application deadline, we will update this posting with a new anticipated application deadline.#LI-GM1Compensation & Benefits DetailsAn employee’s pay position within the salary range may be based on several factors including but not limited to (1) relevant education; qualifications; certifications; and experience; (2) skills, ability, knowledge of the job; (3) performance, cont