Principal PCIe Frontend RTL Lead for Chiplet SoCs
MRL Consulting Group
MRL Consulting Group is seeking a Principal PCIe Sub-system Front-end RTL Lead to drive development of next-generation chiplet-based SoCs for high-performance compute and AI applications. You will own the PCIe microarchitecture and lead RTL integration across PHY, MAC, and Transaction Layer. Collaborate with firmware for register maps and telemetry, guide RTL engineers, and ensure timing closure with Physical Design while driving the PCIe verification strategy with DV teams. #J-18808-Ljbffr MRL Consulting Group
Vacancy posted 1 day ago
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