Senior Clock Architecture & Design Engineer

Senior Clock Architecture & Design Engineer Join a team that defines the heartbeat of next‑generation CPUs. We are looking for a Senior Clock Architecture & Design Engineer to play a pivotal role in developing the clocking architecture for Intel’s next‑generation flagship CPUs. You will work at the cutting edge of semiconductor technology, implementing clock solutions on the industry’s most advanced process nodes. Responsibilities Architect and implement sophisticated clock distribution networks for high‑frequency flagship CPU designs. Pioneer custom clock solutions that push the boundaries of performance and power efficiency. Design breakthrough custom circuits and library cells that enable next‑generation processor capabilities. Develop and optimize advanced clock tree synthesis flows for complex, multi‑billion transistor designs. Collaborate with world‑class architecture, physical design, and validation teams to deliver industry‑leading solutions. Interface with cutting‑edge EDA vendors to shape the future of design automation tools. Behavioral Traits Strong problem ownership and follows designs through architecture, implementation, and signoff. Uses data‑driven decision making to resolve complex technical tradeoffs. Influences design direction through collaboration and technical expertise. Adapts effectively to changing priorities in a fast‑paced development environment. Provides technical guidance or mentorship within project teams. Demonstrates consistency, reliability, and accountability in meeting project commitments. Qualifications Minimum Qualifications Bachelor’s degree in Electrical/Computer Engineering or related STEM field with 5+ years of experience; or Master’s with 3+ years; or PhD with 1+ year. Experience in physical design, clock tree synthesis (CTS), and static timing analysis. Strong background in custom circuits, transistor‑level design, and Spice simulations. Strong programming skills and proficiency in industry‑standard scripting languages. Preferred Qualifications Hands‑on experience in high‑frequency custom clock network design on leading‑edge technology nodes. Experience in clocking architecture, PLL/DLL architecture, and design. Expertise in timing constraint adaptation and timing closure methodologies. Expertise in full‑chip design tools and flows. Compensation Annual Salary Range for U.S. locations: $141,910.00 – $269,100.00 USD. Pay is determined by location, experience, and qualifications. Work Model On‑site presence required in Austin, Texas. EEO Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, sexual orientation, gender identity, national origin, or any other characteristic protected by law. #J-18808-Ljbffr