Principal Signal & Power Engineer (Die to Die and Chiplet Design)

Job ID: 200044776Posted: 2026-07-27Location: United States, North Carolina, RaleighSalary: USD $142,800 - $274,800 per yearEmployment type: Full-TimeWork site: 3 days / week in-officeRole type: Individual ContributorTravel: Less than 25%Profession: Hardware EngineeringDiscipline: Silicon EngineeringCompany: MicrosoftOverviewMicrosoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission.The Compute Silicon & Manufacturing Engineering (CSME) organization within SCHIE is responsible for design, development, manufacturing and packaging of Microsoft's state-of-the-art computer chips, notably the Azure Cobalt. Our solutions provide sustainable strategic advantage to Microsoft and enable our customers to achieve more.As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the Signal and Power Integrity Team team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for seasoned engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure. We are looking for a Principal Signal and Power Integrity Engineer to join the team.#SCHIE #CSMEResponsibilitiesThe SMPE silicon team is seeking a passionate, driven, and intellectually curious computer/electrical engineer to deliver premium-quality designs once considered impossible. We are responsible for delivering cutting-edge, custom IP and SoC designs that can perform complex and high-performance functions in an extremely efficient manner.SIPI engineer for compute and AI SoCs and platforms – Implement strategies for end-to-end design and analysis of D2D interfaces, HBM interfaces, system-level interfaces and associated package technology decisions and tradeoffs.Deliver SIPI solutions that meet the HPC demands across the entire system.Drive future SIPI solutions for chiplet architecture with advanced packaging and advanced silicon nodesDesign, model, and simulate Signal and Power Integrity effects (i.e., incl. IP design, voltage regulator, motherboard, CPU package, silicon, decoupling capacitor solutions, dielectric and copper loss, high-frequency discontinuities, timing budgets, power supply induced jitter, etc.) for data center processors and corresponding platforms to ensure optimized performance. Performs DC, AC and transient simulation to provide a comprehensive prediction of timing/noise margins, and to validate I/O performance from platform to silicon.Work closely with silicon and platform architects, motherboard and package designers, thermal architects and engineers, and power and performance engineers.Drives the execution of architecture solutions across product lines or multiple product groups across teams that account for design trends and future concepts by leveraging cross- functional expertise, industry best practices, and lessons learned from teams working across multiple product linesDrives engineering system design decisions that require collaboration between internal and external stakeholders to account for platform-specific technology decisions and develop system models based on current and anticipated feature/design needs and trade-offs.QualificationsRequired Qualifications: Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experienceOR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experienceOR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experienceOR equivalent experience.Other Requirements:Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter. This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations.  As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable. Preferred Qualifications:MSEE degree with 10 years’ experience in silicon packaging products developmentExperience with power integrity modelling for HPC productsFoundation in advanced packaging technologies as it relates Power integrityExperience with Foundry Silicon technologies, OSAT technologies and Substrate technologiesBSEE degree with minimum 10 years’ experience in silicon/package/system power integrity/deliveryFoundation in the field of Power Integrity and delivery, System design, IP design with knowledge on product development with minimum 7 years’ experience in design and electrical modellingWorking knowledge in the field of end to end system SIPI Design and ArchitectureIndustry knowledge, trends and landscape of technologies to drive development across Silicon-IP, Advanced packaging, Substrate technology, Board technology and Platform designSilicon Engineering IC5 - The typical base pay range for this role across the U.S. is USD $142,800 - $274,800 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $188,000 - $304,200 per year. Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.