RTL Design Engineer
7Rays Semiconductors
We are looking for an experienced CDC/RDC Engineer to work on advanced SoC designs, focusing on Clock Domain Crossing (CDC) and Reset Domain Crossing (RDC) verification and signoff. Responsibilities: Perform CDC and RDC analysis, verification, and signoff for complex SoC designs. Develop and review CDC/RDC constraints, waivers, and methodologies. Analyze and debug clock-domain and reset-domain crossing violations . Work closely with RTL, Design, Physical Design, and Verification teams to resolve issues. Review RTL for proper clock/reset synchronization and identify potential metastability risks. Run CDC/RDC checks and generate detailed reports for design reviews and signoff. Support methodology development, automation, and scripting using Tcl/Python where required. Participate in design reviews and ensure CDC/RDC quality across multiple IPs and SoC blocks. Required Skills: Strong experience in CDC and RDC verification/signoff . Good understanding of clock-domain crossing, reset-domain crossing, metastability, synchronizers, and clock/reset architectures . Strong RTL knowledge with Verilog/SystemVerilog . Experience with CDC/RDC tools such as Synopsys SpyGlass CDC/RDC, VC SpyGlass, Questa CDC, or Cadence tools . Experience working on ASIC/SoC designs and advanced technology nodes . Good debugging and problem-solving skills. #J-18808-Ljbffr
Vacancy posted 3 days ago
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