Senior Silicon Validation Manager - High-Speed SerDes / PCIe

Job Description

Job Description

Senior Silicon Validation Manager - High-Speed SerDes / PCIe

Job Title: Senior Silicon Validation Manager - High-Speed SerDes / PCIe
Location: Santa Clara, CA
Compensation: $150K - $210K base DOE plus bonus and RSUs ($200K - $300K+ total comp.)
Requirements: Post-Silicon Validation, High-Speed SerDes, PCIe and/or Ethernet, UALink, Hardware Validation Management

Position Overview
We are seeking an experienced Senior Silicon Validation Manager to lead a high-performing validation organization focused on high-speed SerDes and PCIe for datacenter silicon and switch ASICs. The role combines technical leadership in silicon bring-up, post-silicon validation, PHY and protocol validation, and test lab infrastructure with people and project management responsibilities. The ideal candidate will own validation strategy, execution, and delivery, enable rapid debug cycles, and ensure silicon meets performance, interoperability, and reliability targets in datacenter environments.

Key Responsibilities

• Define and own silicon validation strategy and plans for high-speed SerDes, PCIe PHY and protocol stacks across pre-silicon to post-silicon bring-up and long-term reliability testing.
• Lead, hire, mentor and grow a cross-functional validation team (hardware, firmware, test automation, and field validation engineers) to meet program milestones and quality targets.
• Coordinate and drive silicon bring-up activities including board bring-up, power sequencing, clocking, SerDes lane training, PHY tuning, and initial functional verification.
• Develop and oversee post-silicon validation programs: stress testing, interoperability (PCIe, Ethernet, UALink), performance characterization, thermal and reliability studies, and regression testing.
• Define and maintain lab infrastructure and test methodologies for high-speed IO testing including BERT, PAM4/NRZ characterization, protocol analyzers, oscilloscopes, TDR/eye analysis, and bit error rate measurements.
• Collaborate closely with SoC/PHY architects, digital and analog designers, firmware teams, system integrators and customers to triage issues, prioritize fixes and close validation loops.
• Establish test automation frameworks, CI systems, and data collection and analysis pipelines to accelerate regression runs and reduce manual debug time.
• Drive functional and protocol compliance testing for PCIe (Gen3/4/5/6 where applicable) and PHY layers, including link training, LTSSM, error handling, and power management scenarios.
• Manage cross-project scheduling, risk assessment, and reporting; escalate issues, propose mitigations, and ensure on-time silicon tapeout and release readiness.
• Enable field validation and customer bring-up activities, traveling as needed to customer sites or partner labs to support complex debug and validation.
• Champion best practices for design-for-test, validation-driven design reviews, and continuous improvement in test coverage, instrumentation and debug efficiency.
• Represent validation progress and technical status to senior leadership and program stakeholders, delivering clear metrics, CI/CD dashboards and go/nogo recommendations.

Qualifications

• Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or related field; PhD is a plus.
• 10+ years of hands-on silicon validation experience with at least 5 years focused on high-speed SerDes, PCIe and PHY validation in datacenter or switch ASIC environments.
• Proven people management experience (3+ years) building and leading high-performance hardware/validation teams, including hiring, mentoring and performance management.
• Deep technical expertise in SerDes architecture and PHY testing, link training, equalization, clocking and jitter analysis.
• Extensive experience with PCIe protocol validation (link bring-up, LTSSM, error handling, training, enumeration) and PCIe PHY characterization.
• Proficiency with post-silicon validation tools and methodologies including BERT, oscilloscopes, protocol analyzers, TDR, eye-diagram analysis and BER testing for high-speed IO.
• Experience with datacenter interconnect technologies such as Ethernet and UALink, and with switch ASIC validation is highly desirable.
• Strong background in silicon bring-up, debug workflows, cross-domain root-cause analysis and coordinating silicon-silicon firmware and software fixes.
• Practical experience building and operating test labs and automation frameworks; scripting in Python, TCL or similar and comfortable with Linux-based test hosts and CI integration.
• Excellent communication and stakeholder management skills; ability to distill complex technical issues into clear action plans and executive summaries.
• Track record of delivering products to schedule while maintaining high quality, and experience defining validation metrics and success criteria.
• Willingness to travel to partner/customer sites and test labs as required; able to work in fast-paced, ambiguous environments and prioritize multiple programs.

Benefits

• Comprehensive medical, dental, and vision plans
• Life insurance and disability plan options
• 401(k)
• RSUs
• ESPP
• Paid company-selected holidays & floating holidays
• PTO - generous time off programs
• Career growth opportunities
  
   

- For this position, you must be currently authorized to work in the United States without the need for sponsorship for a non-immigrant visa. CyberCoders will consider for Employment in the City of Los Angeles qualified Applicants with Criminal Histories in a manner consistent with the requirements of the Los Angeles Fair Chance Initiative for Hiring (Ban the Box) Ordinance.This job was first posted by CyberCoders on 07/14/2026 and applications will be accepted on an ongoing basis until the position is filled or closed. Everforth CyberCoders is proud to be an Equal Opportunity Employer

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, age, sexual orientation, gender identity or expression, national origin, ancestry, citizenship, genetic information, registered domestic partner status, marital status, status as a crime victim, disability, protected veteran status, or any other characteristic protected by law. Our hiring process includes AI screening for keywords and minimum qualifications, and a virtual recruiter as part of the application process. A human recruiter reviews all results. Click here for details on our virtual recruiter .  Everforth CyberCoders will consider qualified applicants with criminal histories in a manner consistent with the requirements of applicable state and local law, including but not limited to the Los Angeles County Fair Chance Ordinance, the San Francisco Fair Chance Ordinance, and the California Fair Chance Act. Everforth CyberCoders is committed to working with and providing reasonable accommodation to individuals with physical and mental disabilities. Individuals needing special assistance or an accommodation while seeking employment can contact a member of our Human Resources team at  View email address on ziprecruiter.com to make arrangements.