Senior Engineer I- Design

Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence.Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.Visit our careers page to see what exciting opportunities and company perks await!Job Description:We are seeking a Senior Engineer I – design to join our team. This role involves RTL design, functional verification, and contributing to next-generation mixed-signal and digital products. The ideal candidate combines strong hardware design fundamentals with modern AI/ML-assisted design methodologies and software skills to improve design productivity and verification quality.ResponsibilitiesDesign, code, and optimize RTL (Verilog/SystemVerilog) for digital blocks and subsystems targeting ASIC implementationDevelop and execute verification plans using UVM/SystemVerilog-based testbenchesWrite constrained-random and directed tests to achieve functional and code coverage targetsApply AI/ML techniques to improve verification closure, coverage analysis, regression optimization, and bug triagingDevelop scripts and automation tools (Python, TCL) to streamline design and verification workflowsCollaborate with architecture, analog, physical design, and software teams to ensure design correctness and integrationPerform lint, CDC, and synthesis checks; resolve issues through the design cycleParticipate in design reviews, specification development, and documentationRequirements/Qualifications:BSEE with course emphasis on microelectronics and 5 years of experience required.Proficiency in Verilog and/or SystemVerilog for RTL designExperience with UVM-based verification environmentsUnderstanding of digital design fundamentals: timing, synthesis constraints, clock domain crossingsProgramming skills in Python; familiarity with TCL or shell scriptingExperience with industry EDA tools (Synopsys, Cadence, or Siemens) will be plus.]Preferred Qualifications:Masters in Electrical EngineeringTravel Time:0% - 25%Physical Attributes:Hearing, Seeing, Talking, Works Around OthersPhysical Requirements:80% Sitting, 10% Standing, 10% WalkingMicrochip Technology Incis an equal opportunity/affirmative action employer. All qualified applicants will receive consideration for employment without regard to sex, gender identity, sexual orientation, race, color, religion, national origin, disability, protected Veteran status, age, or any other characteristic protected by law.For more information on applicable equal employment regulations, please refer to the Know Your Rights: Workplace Discrimination is Illegal Poster.To all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.SummaryLocation: AZ - ChandlerType: Full time