Principal Microelectronics Engineer

Principal Microelectronics Engineer

The successful candidate will support technical and programmatic assessments of technologies, capabilities, materials, equipment, and performers in support of the advancement of the U.S. Defense Industrial Base's (DIB) access to trusted, state-of-the-art microelectronics. The successful candidate will draw upon subject matter expertise across multiple points in the microelectronics supply chain from design through manufacturing, test and integration. This position will work closely with a small team of industry experts, each covering a different aspect of the supply chain and/or technology area, to provide strategic guidance to a broad portfolio of unique and sensitive programs. Additionally, this position will interface and collaborate with a range of engineers, scientists, policy makers, and executives within the government, industry and academia across the country.

Required Qualifications (Must Have's):

• U.S. Citizenship and the willingness and ability to obtain a Secret-level clearance with the U.S. government.
• Bachelors Degree in Electrical Engineering, Computer Engineering, Mechanical Engineering, Manufacturing Engineering, Materials Science, Physics, Computer Science or related technical discipline.
• 12+ years of experience
  • A relevant Masters Degree may be substituted for 2 years of experience (MS w/ 10+ years)
  • A relevant PhD Degree may be substituted for 4 years of experience (PhD w/ 8+ years)
• Excellent verbal and written communication skills.
  • This position requires the ability to brief senior-level executives within the government, industry and academia.
  • The successful candidate will have the ability to write and review technical documents.
• Microelectronics hardware subject matter expertise in at least (1) of the areas listed below AND experience in at least two (2) additional areas listed below:
  • Microelectronics Supply Chain: microelectronics hardware verification/security/trust/assurance, vendor selection/qualification/audit, procurement (i.e. domestic foundry interaction)
  • Wafer-Level Design : digital, RF and/or mixed signal circuit design (schematic, layout), modeling & simulation of key circuit parameters (power, speed, timing, signal integrity, thermal, reliability, etc.)
  • Wafer-Level Fabrication & Test : circuit patterning (i.e. ion implementation), wafer-level packaging (i.e. FOWLP), test/inspection (electrical test & debug, microscopy, metallurgy, failure analysis, repair), back-end processing (ink, grind/polish, dice, sort, inspect, etc.)
  • Chip-Scale Design : digital, RF and/or mixed signal device packaging design/layout (2D-3D, chiplet/UCIe), substrate/interposer design (HDI, HDBU, EMIB), chip attach (epoxy, solder), chip interconnect (chiplet, flipchip, wire/ribbon bonding), modeling & simulation (power, speed, timing, signal integrity, thermal, structural, reliability)
  • Chip-Scale Fabrication & Test: substrate/interposer fabrication, chip attach (epoxy, solder), chip interconnect (flipchip, wire/ribbon bonding), underfill, lidding, balling, tinning/forming, electrical test & debug, inspection & metrology failure analysis
  • Hardware Programming: FPGA (i.e. Verilog, VHDL), Programming (Linux command line/scripting, Python, Java, and C++)

Desired Qualification (Nice to Have's):

• Masters Degree or PhD in Electrical Engineering, Computer Engineering, Mechanical Engineering, Manufacturing Engineering, Materials Science, Physics, Computer Science or related technical discipline.
• Active U.S. Government sponsored Secret Clearance
  • The contract associated with this position has the ability to sponsor and/or maintain higher level clearances if required

TAP Engineering is an Equal Opportunity/Affirmative Action Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status or other characteristics protected by law. Learn more about your rights under Federal EEO laws and supplemental language.