Senior FPGA Engineer (Xilinx) - Video Processing Solution Owner, VHDL, Seattle, WA (On-site)

Job Description

Job Description

Senior FPGA Engineer (Xilinx) – Video Processing Solution Owner, VHDL, Seattle, WA (On-site)

Are you ready to shape the future of video technology? Join as a visionary Senior FPGA Design Engineer and take the lead in architecting breakthrough video processing hardware. This isn’t just another maintenance or verification job—here, you’ll design cutting-edge FPGA solutions from the ground up. Imagine owning every phase, from blue-sky concepts and RTL coding to the thrill of timing closure and seamless system integration.

If you’re energized by a “blank canvas” and excited to see your custom-designed logic powering real-time video innovation, your seat at the table is waiting.

Why should you apply here?

• Established local firm, 39+ years in business.
• 260 employees, 100 plus at this location.
• Engineering and manufacturing are done 100% in-house.
• High-end clients with future products ordered in the pipeline.
• Stable and inflation proof niche.
• A profitable company that’s committed to continuous innovation.
• Stable executive team and engineering leadership.
• Flat organization.

What will you be doing?

• Own the FPGA solution from the first line of code to the final hardware deployment.
• Architect next generation of video technology, building original logic that pushes the boundaries of hardware performance.
• Develop custom high-performance video processing pipelines, including image scaling, color space conversion, and frame rate manipulation.
• Architect complex system-level logic to integrate high-speed interfaces (e.g., PCIe, DDR4, or 10GbE) with proprietary video IP.
• Define and implement clocking strategies and reset logic to ensure robust performance across multiple clock domains.
• Conduct hands-on hardware bring-up and system-level debugging in the lab using logic analyzers and high-speed oscilloscopes to validate RTL performance on live silicon.
• Use VHDL and Verilog for modern digital design.
• Drive timing closure and optimization for high-utilization designs, utilizing advanced synthesis and placement techniques in Xilinx Vivado.
• Own the FPGA micro-architecture by collaborating with cross-functional teams to translate system-level requirements into scalable RTL designs.
• Drive hardware-software integration by interpreting complex schematics to ensure seamless RTL-to-board connectivity and physical layer performance.
• Architect modular FPGA solutions by integrating internal and third-party IP cores while establishing high-performance standards for RTL reusability and efficiency.
• Define and document technical specifications, interface protocols, and timing constraints to ensure robust system-level design integrity.

What are the minimum qualifications?

• 8+ years of FPGA development with proven track record of taking high-level product requirements and architecting original FPGA solutions from the ground up.
• Senior-level command of Xilinx FPGA architectures (UltraScale+, 7-Series) and the Vivado Design Suite, including advanced floor planning and timing closure on high-utilization designs.
• Strong proficiency in writing clean, high-performance Verilog/System Verilog for custom logic, with a focus on minimizing latency and optimizing resource utilization beyond simple IP integration.
• Must be proficient in VHDL and Verilog.
• Extensive experience designing and implementing custom video/audio pipelines for real-time 4K signals; deep knowledge of HDMI, DisplayPort, MIPI CSI-2/DSI-2, and SDI standards.
• Demonstrated ability to architect complex clocking strategies, manage multiple clock domains, and implement robust AXI-streaming and memory-mapped interfaces from scratch.
• Highly proficient in Zynq platform architecture, including the design and configuration of hard/soft IP processor systems and high-speed PL-to-PS data movement (DMA, interrupts, etc.).
• Hands-on leadership in hardware/software integration and bench-level debugging on new silicon, ensuring the final hardware meets the original design specifications.

What will make your résumé stand out?

• Strong knowledge of video compression/decompression algorithms (e.g., H.264/H.265/JPEG-XS) and the ability to implement high-fidelity audio resampling and manipulation directly in RTL.
• Proficiency in embedded Linux environments, including custom scripting for automated FPGA build flows, TCL-based Vivado automation, and driver-level hardware interfacing.
• Experience establishing or maintaining FPGA-centric CI/CD pipelines (e.g., Jenkins, GitLab CI) to automate synthesis, timing analysis, and bitstream generation.
• Exceptional cross-disciplinary collaboration skills with the ability to bridge the gap between software, firmware, and hardware teams; proven success in a high-impact, “multidisciplinary ownership” environment.

Location : Seattle, WA

Schedule: Flexible start and finish time; core hours 9:00-2:00 with the following options:

• 5 days working 8 hours/day
• 4 days working 10 hours/day
• Hybrid, 4 days on-site, 1 day remote

Citizenship : U.S. Citizens or Permanent Residents

Salary: 170K – 210K plus bonus