Formal Verification Engineer

Join AMD's Verification Team

At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we're looking for talent who feel the same: people who want to leave the planet better than they found it, those who don't shy away from humanity's challenges but are determined to help solve them.

AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you're designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward.

The Role

The Infinity Fabric network on the chip verification team is growing and looking for qualified candidates to help verify our configurable switches and die-to-die interconnect. Infinity Fabric is part of every new AMD product being developed for AI/ML, Client, Server, Graphic Accelerator, and Semi-Custom markets.

The Person

Team is seeking a highly skilled and motivated person to join our verification team. In this role, you will drive formal verification efforts across complex hardware designs, applying rigorous mathematical methods to prove design correctness and find corner-case bugs that escape simulation. You will serve as a subject matter expert in formal verification methodologies, mentor junior engineers, and collaborate with RTL designers, simulation-based verification engineers, and architects to shift verification left and improve overall design quality.

Key Responsibilities

• Develop and execute formal verification strategies using VC Formal and/or JasperGold for property checking (FPV), connectivity checking (CC), register verification (FRV), and sequential equivalence checking (SEQ)
• Write, review, and debug SystemVerilog Assertions (SVA) — including assumptions, assertions, and cover properties — to verify complex design behaviors
• Drive convergence on formal proofs by applying abstraction techniques, complexity reduction strategies, and assume-guarantee reasoning
• Collaborate with RTL designers and architects to define verification plans that incorporate formal methods alongside simulation-based approaches
• Identify and pursue opportunities to apply formal verification to new design blocks, championing a "formal-first" or "shift-left" verification strategy
• Develop reusable formal verification infrastructure, including constraint libraries, parameterized property templates, and automated regression flows
• Mentor and guide MTS and junior engineers in formal verification techniques and best practices

Preferred Experience

• Hands-on experience with VC Formal (Synopsys) and/or JasperGold (Cadence)
• Strong proficiency in SystemVerilog Assertions (SVA) and formal property specification
• Experience with formal verification applications: FPV, connectivity checking, register verification, equivalence checking, and coverage analysis
• Familiarity with scripting languages (TCL, Python, Perl) for flow automation
• Minimum 8+ years of experience in design verification with a strong focus on formal verification

Academic Credentials

• Bachelors or Masters degree in computer engineering/Electrical Engineering

Location

Austin, TX; Boston, MA and Santa Clara, CA

This role is not eligible for visa sponsorship.