Advanced SerDes & Analog/Mixed-Signal IC Design Intern - Summer 2027

Why join Upscale, Inc.

Upscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $500M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads. We focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact. If you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. About the Role Upscale AI is developing next-generation high-speed connectivity solutions for AI infrastructure and data centers. We are looking for highly motivated summer interns to work alongside our experienced engineering team on advanced SerDes and analog/mixed-signal integrated circuit design. This internship offers hands-on opportunities to explore challenging problems at the intersection of high-speed circuit design, digital signal processing, and AI-driven engineering methodologies. Depending on your background and interests, you may contribute to one or more of the following areas: High-Speed ADC Design and Modeling:

Research and develop high-performance ADC architectures for next-generation SerDes receivers, including sampling architectures, time-interleaved ADCs, calibration techniques, and optimization of speed, resolution, power, and linearity. Foundation IP Development:

Contribute to the design, modeling, characterization, and optimization of foundation analog/mixed-signal IP blocks that enable next-generation SerDes, including clocking, data conversion, calibration, and related circuit building blocks. AI-Driven Circuit Design:

Develop and apply AI/ML techniques to accelerate circuit design, optimization, modeling, and verification. Explore automated design-space exploration, intelligent parameter optimization, surrogate modeling, and AI-assisted engineering workflows. Ultra-Low-Jitter PLL Design and Modeling:

Explore advanced PLL architectures for high-speed communication systems, including low-jitter clock generation, digitally intensive PLL architecture and design. Investigate phase-noise performance, jitter optimization, and high-precision modeling of the PLL in the digital domain. What You’ll Do Collaborate with experienced engineers to investigate challenging circuit and system-level design problems. Develop analytical models, behavioral simulations, and circuit-level simulations to evaluate new architectures and design approaches. Build scripts and tools to automate simulation, data analysis, optimization, and design workflows. Explore novel algorithms and circuit techniques to improve performance, power efficiency, robustness, and design productivity. Present technical findings, simulation results, and design recommendations to the engineering team. Where appropriate, contribute to circuit implementation, verification, characterization, or silicon measurement activities. Qualifications: Currently pursuing an M.S. or Ph.D. in Electrical Engineering, Computer Engineering, or a related field. Strong fundamentals in analog and mixed-signal circuit design, communication systems, signal processing, or related areas. Experience with circuit simulation, numerical analysis, or engineering computation. Proficiency in Python, MATLAB, or similar tools for modeling, automation, and data analysis. Strong analytical and problem-solving skills, with the ability to independently investigate technical challenges. Preferred Qualifications Coursework, research, or project experience in one or more of the following:

AI/ML applications in EDA, circuit design, or engineering optimization. High-speed ADCs, data converters, or receiver architectures. PLLs, clock generation, phase noise, jitter analysis, or DTC/TDC-based digital PLLs. High-speed SerDes, wireline transceivers, or high-speed communication systems. Analog/mixed-signal foundation IP development and circuit optimization.

Familiarity with SPICE-based circuit simulators, MATLAB/Python modeling, RTL, or digital signal processing. Experience with optimization algorithms, machine learning, behavioral modeling, or automated verification. A strong track record of research, technical projects, publications, or hands-on implementation. What You’ll Gain Work on advanced connectivity technologies for AI data center infrastructure. Gain exposure to real-world circuit design challenges at the intersection of architecture, algorithms, and transistor-level implementation. Learn from experienced engineers developing next-generation high-speed analog and mixed-signal IP. Own a well-defined technical project with measurable engineering outcomes and opportunities to present your work. We welcome candidates who are curious, technically ambitious, and eager to turn innovative ideas into practical silicon solutions. \n\n

$20 - $28 an hour \n

Where you fall within that range depends on your experience, skills, and impact—we benchmark against internal levels to keep things fair and consistent. Equal Opportunity Upscale, Inc., is building a team that reflects a wide range of perspectives, backgrounds, and experiences. We’re proud to be an Equal Opportunity Employer and consider all qualified applicants regardless of race, color, religion, national origin, sex, sexual orientation, gender identity, disability, or veteran status. Accessibility & Accommodations We’re committed to making our hiring process accessible to everyone. If you need accommodations at any stage, just reach out to us at

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