Design Engineer II

Responsibilities Implement RTL-to-GDSII for in-house IP and external customer designs. Develop, automate, and maintain EDA flows and scripts for physical implementation. Develop TFM to optimize PPA for IPs and soft controllers. Characterize and optimize flow for performance-and power-oriented best-in-class IP cores on advanced process nodes at TSMC, Intel, Samsung, and Rapidus. Implement digital design using Cadence EDA tools: Genus, Innovus, Conformal, Litmus, Tempus, Voltus, Certus, Pegasus, and other backend tools. Qualifications MS/MTech/BE/BTech in Electronics with 2+ years of experience. Experience in physical design within an ASIC design environment. Knowledge of the complete ASIC design flow, including synthesis, physical design, timing analysis, power analysis, and formal verification. Strong scripting skills in Python and Tcl. Excellent leadership, communication, analytical, and problem-solving skills. Self-motivated and a good team player. Compensation Annual salary range (California): $87,500 to $162,500. Eligible for incentive compensation: bonus, equity, and benefits. Benefits Paid vacation and paid holidays. 401(k) plan with employer match. Employee stock purchase plan. Medical, dental, and vision plan options. Equal Employment Opportunity Statement Cadence is a proud equal-opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class. #J-18808-Ljbffr