PCB Layout Designer

PCB Layout Designer

Location: Fremont, CA (On-Site) Mon - Friday 8 am - 5 pm, Regular shift

Role Overview

• The position is primarily a PCB Layout Designer role.
• Role is on-site 5 days a week at Fremont Lam campus.

Primary Responsibilities

• Perform PCB layout work using Cadence Allegro (80-90% of role).
• Collaborate with other teams for schematic reviews, documentation, and updating BKM (Best Known Methods).
• Occasionally assist with cross-functional design efforts (~10–20% of time).
• Conduct and improve Design Rule Checks (DRC) and other quality control measures to reduce post-release errors.

Tools & Technical Details

• CAD Tool: Cadence Allegro (currently version 22.1, previously 17.4).
• Must have strong experience with Allegro; ok if they have only used previous versions.
• No flex cable designs: focus is on traditional PCB types.
• Boards range from 2 to 40 layers, including digital, analog, and power circuits.
• Common connectors: D-Subs (9-pin, 15-pin), Ethernet (hardened), and industrial-grade coaxials.

Experience Requirements

• Minimum: 5 years of PCB layout experience.
• Open to: Senior-level designers (15–20+ years).
• Candidates nearing retirement are acceptable but must commit to at least 2 years.
• Industry background is flexible — semiconductor experience is not required but is preferred. Aerospace, medical, or other high-tech PCB experience is acceptable.

Challenges & Team Focus

• Primary Challenge: Improving design quality and minimizing rework.
• Goal: Ensure thorough QC and DRC before release to avoid client-reported issues.
• Department is focused on releasing boards "right the first time."