Fpga Engineer

FPGA Engineer Digital Engineer on‑site in San Diego, CA. Job Description Join our team operating at the forefront of technology and innovation, contributing to digital logic verification for software‑defined radio systems. We value bold ideas, curiosity, and a team‑based environment that encourages intellectual growth. Responsibilities Provide hands‑on technical leadership and mentor a team of 2‑4 VHDL verification engineers. Define and maintain digital logic design verification frameworks and architectures for software‑defined radio systems. Develop verification plans based on digital logic design requirements and specifications. Simulate and verify FPGA logic designs, requirements, and perform system validation. Analyze and debug simulation failures, determine root causes of bugs, and work with designers to resolve issues. Perform regression testing and generate verification metrics and reporting. Operate in a team environment with 5‑7 engineers. Essential Skills 12 or more years of professional technical experience. Experience in VHDL design and verification methodologies for DoD communications systems. FPGA deployable product process experience, including requirements definition, conceptual design, detailed design, verification, and production release. Experience with technical management of tasks, forecasting, and estimating schedules to ensure completion to meet schedule and quality standards. Strong analytical skills and the ability to prioritize assignments according to program goals. Ability to coordinate and communicate effectively with members of cross‑functional teams and program management. Experience developing verification plans, functional tests, test benches, and bus functional models. Experience using Siemens Questa Simulator. Must be able to obtain and maintain a Security Clearance. Additional Skills & Qualifications Active Security Clearance is preferred. Experience in leading a team with various levels of experience and skills. Experience with the management of cost and metric reporting. Experience with functional verification methodology using OSVVM for the full lifecycle of products. Experience with scripting languages for verification automation in a Linux environment, including Perl, TCL, Bash, and Makefile. Experience using Siemens formal applications such as Lint, Inspect, and CDC. Ability to hold special access program clearances. Work Environment This position is based on‑site in San Diego, CA, and involves working in a collaborative team environment with 5‑7 engineers. The role requires balancing individual contributor responsibilities with technical leadership in fast‑paced, program‑driven settings. The work involves exposure to DoD, defense systems, communications systems, or regulated environments. The dress code is professional, and the position requires U.S. Citizenship with the ability to obtain or maintain a security clearance. Job Type & Location This is a Contract position based out of San Diego, CA. Application Deadline This position is anticipated to close on Jun 10, 2026. Equal Opportunity Employer The company is an equal opportunity employer and will consider all applications without regard to race, sex, age, color, religion, national origin, veteran status, disability, sexual orientation, gender identity, genetic information or any characteristic protected by law. Pay and Benefits The pay range for this position is $125.00 - $160.00/hr. Eligibility requirements apply to some benefits and may depend on your job classification and length of employment. Benefits are subject to change and may be subject to specific elections, plan, or program terms. If eligible, the benefits available for this temporary role may include: Medical, dental & vision Critical Illness, Accident, and Hospital 401(k) Retirement Plan – Pre‑tax and Roth post‑tax contributions available Life Insurance (Voluntary Life & AD&D for the employee and dependents) Short and long‑term disability Health Spending Account (HSA) Transportation benefits Employee Assistance Program Time Off/Leave (PTO, Vacation or Sick Leave) #J-18808-Ljbffr Actalent