Senior Verification Engineer - HDL, FPGA & SerDes Innovation
Lattice
Lattice in Idaho is seeking a Design Verification Engineer to enhance its R&D organization. This role involves developing test plans, creating verification environments, and debugging DUT tests. Candidates should have strong HDL skills, experience in high-speed protocols, and 5+ years in SystemVerilog/UVM. A proactive approach and adaptability in a dynamic setting are essential. This is a great opportunity for those looking to grow in their careers within a collaborative team. #J-18808-Ljbffr
Vacancy posted 9 hours ago
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