Principal Verification Engineer

Please Note: To conform with the United States Government Space Technology Export Regulations the applicant must be a U.S. citizen lawful permanent resident of the U.S. conditional resident asylee or refugee (protected individuals as defined by 8 U.S.C. 1324b(a)(3)) or eligible to obtain the required authorizations from the U.S. Department of State.

This position is with Jariet Technologies Inc. a subsidiary of CesiumAstro. Jariet is developing breakthrough technologies to permit digital communications technology to be applied at micro/mm-Wave speeds using standard CMOS processes. Jariet is well positioned to provide ASIC products into emerging markets in multi-antenna beamforming communications systems and wireless infrastructure as well as digital deployments into microwave point-to-point links and radar systems. We are actively seeking passionate collaborative energetic and forward-thinking individuals to join our team.

The Design Verification team is growing and has a need for a top talent principal level ASIC functional verification engineer. The position may also involve team or project this role you will be responsible for the development of leading edge verification methodologies for complex high speed digital communication SoCs.

JOB DUTIES AND RESPONSIBILITIES

• Design and implement verification test bench infrastructure and test cases for system chip and block level verification using the latest tools and SystemVerilog class libraries such as OVM UVM and VMM.
• Implement Pseudo-random and functional coverage verification methodologies.
• Develop functional test and verification plans.
• Work closely with the VLSI Design team to plan and implement design verification strategies.

JOB REQUIREMENTS AND MINIMUM QUALIFICATIONS

• Minimum of 10 years of relevant experience with a Bachelor of Science (BS) degree in Computer Science Electrical Engineering or Computer Engineering or related engineering discipline or a minimum of 8 years of experience with a Masters degree.
• Proficiency in Pseudo-random and functional coverage verification methodologies.
• Strong working knowledge of SystemVerilog and its class libraries such as UVM OVM or VMM.
• Experience with SVA PSL or OVL assertions.
• Excellent written and verbal communication skills.

PREFERRED EXPERIENCE

• Formal model checking tools (e.g. Cadence IFV Jasper).
• Experience with DSP and digital communications.

$165000 - $199000 a year

CesiumAstro considers several factors when extending an offer including but not limited to the role and associated responsibilities a candidates work experience education/training and key skills. Full-time employment offers include company stock options and a generous benefits package including health dental vision HSA FSA life disability and retirement plans.

CesiumAstro is an Equal Opportunity employer. All qualified applicants will receive consideration for employment without regard torace color religion sex national origin disability protected Veteran Status or any other characteristic protected by applicable federal state or local law.

Please note: CesiumAstro does not accept unsolicited resumes from contract agencies or search firms. Any unsolicited resumes submitted to our website or to CesiumAstro team members will be considered property of CesiumAstro and we will not be obligated to pay any referral fees.

We may use artificial intelligence (AI) tools to support parts of the hiring process such as reviewing applications analyzing resumes or assessing responses and identifying potential inconsistencies or verification signals in application materials based on available information. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed please contact us.

Required Experience:

Staff IC