Senior Principal ASIC Design Engineer
Hypres
Responsibilities:
- Working with project teams to define the generation of design specifications and requirements
- Developing architecture and executing the plans
- Maintaining involvement in all phases of design, including:
- RTL implementation
- Synthesis
- Timing analysis
- Physical design and verification
- Floor planning and partitioning
- Place and route
- Clock domain crossing analysis
- Equivalence checking
- PPA (power/performance/area) optimizations
- Documentation.
- Designing semiconductor and superconductor integrated circuits
- Driving innovation, providing organizational leadership to expand business opportunities.
- Master's Degree or Ph.D in Computer Science or Electrical Engineering
- 10 years of relevant work experience
- Successful execution of ASICs from product definition to production release
- Ability to provide mentorship and guidance to junior and senior engineers
- Experience with RTL, Verilog, System Verilog, synthesis, full chip floor-planning, P&R, formal verification, clock tree insertion and timing closure
- Multiple successful tapeouts
- Experience with DSP hardware implementations on ASICs (preferred but not mandatory)
- Familiarity with superconductor integrated circuit design (preferred but not mandatory)
HYPRES is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, gender, gender identity or expression, sexual orientation, national origin, genetics, disability, age or veteran status.
Vacancy posted 3 days ago
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