Staff Engineer Digital OSVVM Verification

Key Details Relocation Assistance: Relocation assistance may be available. Clearance Required at Start: Yes Clearance Type: Secret Travel: Yes, 10% of the time Description At Northrop Grumman, our employees have incredible opportunities to work on revolutionary systems that impact people’s lives around the world today, and for generations to come. Our pioneering and inventive spirit has enabled us to be at the forefront of many technological advancements in our nation’s history. We are looking for you to join our team as a Sr Principal Engineer Digital based out of San Diego, CA. Our Advanced Digital Design organization creates the next generation of communications and signal processing systems and will take ideas from concept to working systems aboard the world’s most advanced platforms right here in Denver, San Diego. We seek degreed electrical or computer engineering engineers with hands‑on experience in FPGA Verification with VHDL. Responsibilities You will be responsible for digital designs associated with multi‑function software‑defined radios. Systems include state‑of‑the‑art radios and test equipment for military applications. This is a dual level requisition which can be filled as a Sr. Principal Digital Engineer. This position is contingent upon obtaining a DoD secret clearance and customer approval. Qualifications Basic Qualifications: 12+ years of relevant experience with a Bachelor of Science in Electrical Engineering (BSEE) or Computer Engineering (BSCE); 10 years of relevant experience with a Masters; 8 years of relevant experience with a PhD. Experience with developing verification plans, test benches, and verification components using OSVVM. Hands‑on experience in VHDL design, verification, simulation, and testing of AMD and/or Intel FPGAs. Experience with Electronic Design Automation (EDA) Tools for FPGA development: Vivado, Quartus, Questa Simulator. Demonstrated ability to work independently, taking initiative to complete tasks with minimal supervision while contributing to team success. Experience with board or system level debug using common test equipment. Must have the ability to obtain and maintain DOD Secret Clearance. Preferred Qualifications: Knowledgeable in physical constraints, timing constraints, and achieving timing closure. Experience with developing FPGA requirements and be able to show traceability to requirements and technical references. Proven experience creating design‑assurance deliverables and assembling technical data packages. Familiar with multilayer board design, high‑speed interfaces, and RF communication systems. Salary Primary Level Salary Range: $194,700.00 - $292,100.00. The above salary range represents a general guideline; however Northrop Grumman considers a number of factors when determining base salary offers, such as the scope and responsibilities of the position and the candidate’s experience, education, skills, and current market conditions. Benefits Employees may be eligible for overtime, shift differential, and a discretionary bonus in addition to base pay. Annual bonuses reward individual contributions and allow employees to share in company results. Employees in Vice President or Director positions may be eligible for long‑term incentives. Northrop Grumman provides a variety of benefits including health insurance coverage, life and disability insurance, a savings plan, company‑paid holidays, and paid time off (PTO) for vacation and/or personal business. Equal Opportunity Statement Northrop Grumman is an Equal Opportunity Employer, making decisions without regard to race, color, religion, creed, sex, sexual orientation, gender identity, marital status, national origin, age, veteran status, disability, or any other protected class. For our complete EEO and pay transparency statement, please visit . U.S. Citizenship is required for all positions with a government clearance and certain other restricted positions. Job Category: Engineering #J-18808-Ljbffr Northrop Grumman Corp. (JP)