Research Scientist Loop Engineering and AI Infrastructure

About the Company:

At SK hynix memory solutions were at the forefront of semiconductor innovation developing advanced memory solutions that power everything from smartphones to data centers. As a global leader in NAND flash technology and memory solutions we drive the evolution of advancing mobile technology empowering cloud computing and pioneering future technologies. Our cutting-edge memory technologies are essential in todays most advanced electronic devices and IT infrastructure enabling enhanced performance and user experiences across the digital landscape.

Were looking for innovative minds to join our mission of shaping the future of technology. At SK hynix memory solutions you will be part of a team thats pioneering breakthrough memory solutions while maintaining a strong commitment to sustainability. Were not just adapting to technological change were driving it with significant investments in artificial intelligence machine learning and eco-friendly solutions and operational practices. As we continue to expand our market presence and push the boundaries of whats possible in semiconductor technology we invite you to be part of our journey to creating the next generation of memory solutions that will define the future of computing.

About the Role:

We are hiring a full-time research scientist. Depending on your qualifications the job is loop engineering AI infrastructure research or both.

Loop engineering is the design and study of closed-loop flows that automate optimize and explore SoC designs. These are AI-assisted hardware/software co-design flows. CHIA from UC Berkeley is one example of a framework you may use.

AI infrastructure research is full-stack design and optimization of AI systems from storage devices to the host: how memory-device noise affects AI performance where the system bottlenecks and which compute-memory architectures are worth building.

You will own the research questions methods and written results.

What you will do:

• Establish best practices for SoC design automation optimization and design-space exploration and make them the way the team runs design studies.
• Design and implement co-design loops whose steps run SoC tools simulators software builds physical-design feedback and AI agents and whose outputs feed the next iteration.
• Build those flows with the languages and tools the study needs including Chisel and XLS simulators software builds and ASIC or FPGA CAD.
• Measure whether the designs a loop produces are correct and compare them on power speed silicon area or how well the target workload runs. Record which design was chosen what the search cost and enough detail that someone else can rerun the study and see why a run failed.

Research: AI infrastructure:

• Study AI system design from storage and memory devices through controllers interconnects and the host software path used by training and inference.
• Measure how device noise and non-idealities (read and write noise variation retention disturb and error rates) affect model quality tail latency throughput and energy.
• Quantify bottlenecks in capacity bandwidth latency power and data movement and state what they imply for architecture.
• Evaluate compute-memory architectures such as near-memory and in-memory compute computational storage and disaggregated memory.

What you bring:

• Bachelors masters or Ph.D. in electrical engineering computer engineering or computer science. A bachelors degree should include research depth in computer architecture computer systems VLSI or electronic design automation.
• A record of taking a research question to a measured written result.
• Strong in Python.

For a loop-engineering assignment:

• Experience automating an SoC RTL or physical-design flow including design-space exploration or closed-loop optimization.
• Ability to design interfaces between design tools so a flow can be reused.

For an AI infrastructure assignment:

• Research on the path from storage or memory devices to a host running an AI workload and on how device behavior system bottlenecks or compute-memory architecture affect AI performance.

Preferred Qualifications:

• Hands-on experience with an AI-assisted hardware/software co-design loop framework such as CHIA or with another agentic or scripted flow.
• Proficiency with Chisel XLS or RISC-V SoC integration and with RTL simulation or FPGA prototyping.
• Experience with commercial ASIC flows and with reading timing power and area reports.
• Experience with architecture simulators.
• Background in memory or storage reliability: device noise ECC endurance or error models.
• Papers or patents in computer architecture VLSI CAD or hardware/software co-design.

What success looks like:

In the first year a loop-engineering hire produces a reusable co-design loop for an SoC decision and a written best practice. An AI infrastructure hire produces a result that ties a bottleneck a memory-device noise effect or a compute-memory architecture to host-level AI performance. A hire for both produces both.

COMPENSATION: $000000/yr - $000000/yr

REGARDING COMPENSATION:

SK hynix memory solutions America Inc. offers you the opportunity to apply your skills to exciting projects while working with innovative teams. Our compensation package is complimented by a generous benefits package including medical dental vision life insurance and a company 401(k) match as well as cafeteria onsite gym and much more. If you are motivated by technical challenges we offer a collaborative work environment that encourages career growth.

The salary offered to a selected candidate will be tailored based on several factors including the location job grade relevant knowledge skills and experience. We also take into account the internal equity among our current team members to ensure fairness and competitiveness.

Required Experience:

IC