US_West | Graphic User interface Designer / UX / ergonomics_L3

Description:

Possible 3 Month CTH | No Fees | Do Not Re-Post | Confidential
Submit candidates under their legal name and use only Capgemini template


Role: Design Verification Engineer
Work location: San Francisco, California (Remote)
Start date: Immediate availability
Background check MANDATORY
Request ID: 10914336, 10962695


JOB DESCRIPTION


Design Verification Engineer
As a Design Verification Engineer (DVE), you will be a member of a small team which owns verification of our graphics IP's and SoC's in prototype and SoC design environment. Your work will establish functional and performance benchmarks for our existing graphics solutions and feed directly into solutions. To achieve this, you will lead the definition, execution and continuous improvement of a robust design verification (DV) methodology and tools flow across different verification platforms. Your responsibilities will extend to IP and SoC design verification (DV), from the RTL level to emulation, resulting in fully functional and performant IP's/SoC's. This will require working closely with Graphics Architects, Chip/SoC Leads, IP designers, Systems/Validation Leads as well as external SoC design partners.
Responsibilities
• Develop and implement test/verification plans, methodologies and tool flows for graphics IPs
• Define and implement IP/SoC verification plans, test benches and simulation/emulation coverage leading to fully functional and performant graphics IPs/SoCs
• Drive DV plan development and execution through post-silicon bringup/validation
• Define and implement system/integration tests
• Work with cross functional teams to identify best verification methodology
• Build or leverage highly automated & flexible DV environments/flows spanning prototypes, SoC's and hardware emulation platforms
• Support integration of IP block tests into larger SoC environment tests
Minimum Qualifications
• BS Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience
• 6+ years of experience in RTL verification for FPGAs or ASICs
• Experience with SystemVerilog UVM testbenches, coverage analysis, and SVA
• Experience with FPGA and SoC design flows, tools and methodology
• Experience with industry standard RTL simulators, emulators and waveform debugging tools
• Experience with Python3 scripting
Preferred Qualifications
• Master's degree in Electrical Engineering, Computer Engineering or Computer Science
• Experience as an RTL designer
• Experience in development environment creation from scratch
• Experience in verifying designs generated with high level synthesis
• Experience with complex SoCs
• Experience with development of fully automated flows from specification to fully verified designs
• Experience with Software/Hardware Co-simulation (DPI/VPI)
• Experience with verification of high speed interfaces like PCIe, USB, MIPI
• Experience with on-chip bus protocols (AXI, AXI-Lite, AHB)
• Experience with post-silicon lab/bench test/validation
• Knowledge of formal verification


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**VIDEO INTERVIEW IS MANDATORY


- ERM
Daycira Salguero| Capgemini North America
Tel.: View phone number on click.appcast.io