Design Verification Engineer - Low-Latency FPGA/ASIC
Hudson River Trading
Hudson River Trading (HRT) seeks a Design Verification engineer to craft testbenches and verification environments for high-performance hardware across FPGA/ASIC platforms. You will work with RTL teams, write Python-based tests, and contribute to open-source tooling like Cocotb. Join a fast-paced team focused on correctness and robustness in a real-time trading environment, with opportunities to influence verification strategies and tooling choices. #J-18808-Ljbffr
Vacancy posted 4 days ago
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