SoC Architect

Opticore is seeking an experienced SoC Architect to lead the definition and development of next-generation custom silicon for our OPU (Optical Processing Unit) compute platform. This role owns the architecture that turns the OPU into a complete, production-ready system: the memory hierarchy, interconnects, and system-level tradeoffs that determine real-world performance, power, and cost. You will work cross-functionally with internal design, verification, and software teams, as well as external silicon and IP partners, to translate platform requirements into a scalable SoC architecture, driving execution from concept through silicon delivery. What You'll Do Define the architecture and technical roadmap for custom SoCs built around the OPU compute platform. Architect the memory subsystem (on-chip SRAM, shared cache hierarchy, and high-bandwidth external memory such as HBM and DDR) sized for the throughput and latency demands of OPU workloads. Define system interconnects (AXI, NoC, chiplet-to-chiplet links) connecting the OPU, memory, and surrounding system blocks. Drive system-level tradeoff analysis across compute, memory, interconnect, power, thermal, and cost constraints. Develop strategies for data tiling, buffering, and task mapping to maximize OPU utilization and minimize data‑movement overhead. Lead hardware/software co‑design efforts to maximize performance per watt and end‑to‑end system efficiency. Partner with external silicon vendors, IP providers, and manufacturing partners to execute development plans. Guide implementation teams through microarchitecture, RTL development, validation, and bring‑up phases. Define debug, trace, and performance‑monitoring features across the compute and memory subsystem. Operate effectively in agile development environments and help teams deliver against aggressive schedules and milestones. You Might Thrive in This Role If You have proven experience defining and delivering complex SoC or ASIC architectures from concept to production. You have deep understanding of AI/ML compute architectures, memory‑bound workloads, and energy‑efficient compute design. You have strong knowledge of SoC subsystems including memory hierarchies (including HBM), interconnects, and power management. You have experience working with both internal engineering organizations and external strategic partners. You can lead cross‑functional teams in fast‑paced, execution‑driven environments. You communicate clearly and can influence technical direction across organizations. Preferred Qualifications Experience with chiplet‑based architectures and interconnect standards such as UCIe, UALink, or HBM. Background in performance modeling, silicon cost optimization, and workload‑driven architecture. Familiarity with advanced process nodes and modern semiconductor development flows. Proven success taking a compute‑heavy AI or HPC SoC through first silicon. Understanding of low‑level data movement and memory optimization for AI compute workloads. #J-18808-Ljbffr