Analog layout Engineer

:Knowledge of analog/mixed-signal IP (e.g., SERDES PHY, transmitter and receiver, PLL, DDR PHY, ADCs, DACs, LDOs, etc. )Experienced working with the circuit designer or layout lead to plan/schedule work and negotiate any layout trade-offs as neede dReviewing and analyzing floor-plans and complex circuits with circuit designer sRunning complete set of design verification tools availabl eGreat understanding and experience using advanced CAD tools and mask design knowledge to deliver correct and robust layout that meet stringent matching performance, area and power requirement sExperienced in crafting well-matched, low noise, and low power analog blocks consisting of transistors, resistors, capacitors, pad IO's, ESD structures, etc .Must understand issues of IR drop, RC delay, electro-migration, self-heating and coupling capacitanc eMust recognize failure prone circuit and layout structures, have experience with analog and DFM standard methodologies, and enthusiastically work with circuit designer or layout lead for the best approach to problem sHigh level of proficiency in interpretation of CALIBRE DRC, ERC, LVS, etc., report sKnowledge of CADENCE Virtuoso and MENTOR GRAPHICS layout tool #J-18808-Ljbffr Programmers.io