Gate-level Noise (Signal Integrity) / STA CAD Engineer

Imagine what you could do here! At Apple, new ideas have a way of becoming phenomenal products very quickly. Do you want to bring passion and dedication to your job? There's no telling what you could accomplish at Apple. The people who work here have reinvented entire industries with Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices - we continue to strengthen our commitment to leave the world better than we found it!
As a member of the CAD group, you will support the gate-level glitch noise and static timing analysis (STA) methodologies that ensure the signal integrity and robustness of Apple silicon across advanced technology nodes. In this role, you will learn and apply sign-off methodologies, margin models, and production CAD flows for crosstalk glitch and timing closure using industry-standard tools, under the guidance of senior engineers. You will work closely with CAD and physical design teams, assist with tool qualifications, help execute tapeout ECO tasks, and gain exposure to modern automation - including AI-agent workflows - used to scale analysis across our largest SOC designs.