Senior Staff Power Performance Architect Accelerator Design

Location Hybrid, working onsite at our Santa Clara, Ca headquarters 3-5 days per week. What You Will Do Responsible for pre-silicon power estimation of the blocks in design. The responsibility includes both RTL power estimation as well as Physical design power estimation of the blocks. You will work with front-end and DV engineers to identify the windows of power activity in the design. You will work with the RTL team to ensure that the feedback from the estimation is implemented and results in optimizing power. Build an architectural power estimation tool for AI workloads to compute power based on system configuration and die level metrics. This will include workload profiling using external/internal memory size, bandwidth, gate counts, of compute/memory blocks. You will work with frontend architects and backend design to compile the performance monitor availability, system requirements, usage etc. Your analysis will be used to improve the hardware capabilities as well as die modifications to include performance monitoring/boosting features. You will work with the frontend team to integrate the feedback from the analysis into the design. Design of micro-architecture and RTL, synthesis, logic and physical power performance verification using leading edge CAD tools and semiconductor process technologies. Design and Implement performance enabling and power saving/monitoring functions that enable efficient design, test and debug. Participate in silicon bring-up and validation. What You Will Bring Master’s degree in electrical engineering, Computer Engineering or Computer Science. Understand Power, Performance, micro-architecture, RTL, Physical design, focused on digital system and IC design. Good understanding of ASIC design flow including RTL design, verification, logic synthesis and physical design. Exposure to Power estimation, Performance metrics is valuable. Additional exposure to different system/IC design points such as TDP, PMAX, EDP, Peak, Average is valuable. Familiarity with DFS, DVFS, AFS, AVFS, is valuable. Familiarity with PDN, resonance, Z(f), droop analysis, is valuable. Required Qualifications IC design Fundamentals: Understanding of IC design flow (Arch > uarch > RTL > Schematic > Layout > Verification > Fabrication > HVM) and familiarity with at least one EDA tool for power estimation. Comfortable in traversing and context switching between RTL, Physical design, and Automation. Improve design execution productivity by building script utilities and deploy usage across the design team. Programming Skills: Comfortable with TCL, Python. Experience with libraries, APIs, data parsing, and algorithmic thinking. Strong willingness to contribute and be self‑motivated. Ready to pick up new design activities, modify things and iterate at a fast cadence, use engineering judgement to make design calls, prefer action over advice. Equal Opportunity Employment Policy d-Matrix is proud to be an equal opportunity workplace and affirmative action employer. We’re committed to fostering an inclusive environment where everyone feels welcomed and empowered to do their best work. We hire the best talent for our teams, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. Our focus is on hiring teammates with humble expertise, kindness, dedication and a willingness to embrace challenges and learn together every day. #J-18808-Ljbffr Entrada Ventures