ASIC Design Engineer, STA

The application window is expected to close on: 04/30/2026 Meet the Team Join the Cisco Silicon One team in developing a unified silicon architecture for web scale and service provider networks. Cisco’s silicon team provides a unique experience for ASIC engineers by combining the resources offered by a large multi-geography silicon organization and a large campus (with onsite gym, healthcare, and café, social interest groups, and philanthropy), with the startup culture and breadth of growth opportunities that working in a smaller ASIC team can provide. Within this role, you'll work on closing timing at block, sub-chip, and full-chip levels, performing quality checks such as setup, hold, transition, and noise, while handling ECO tasks. Your Impact As an ASIC Design Engineer on the STA team, you will play a pivotal role in extraction and static timing analysis (STA) flow development, convergence strategies, and correlation between PNR, Spice, and STA, while working alongside the Physical Design team. Develop methodologies, guidelines, and checklists to streamline STA work. Resolve design and flow issues. Drive execution to ensure progress and accuracy. Minimum Qualifications Bachelor’s degree in Electrical or Computer engineering and 5+ years of ASIC Design experience, or Master's degree in Electrical or Computer Engineering and 3+ years of experience, or PhD + 0 years of experience. Experience with Verilog/SystemVerilog programming. Preferred Qualifications Prior STA experience is a plus. Strong written and verbal communication skills. #J-18808-Ljbffr