Senior FPGA Design Engineer

Senior Fpga & Firmware Engineer - SdrScottsdale, Arizona, United StatesJoin Axon and be a force for good.At Axon, we're on a mission to protect life. We're explorers, pursuing society's most critical safety and justice issues with our ecosystem of devices and cloud software. Like our products, we work better together. We connect with candor and care, seeking out diverse perspectives from our customers, communities and each other. Life at Axon is fast-paced, challenging and meaningful. Here, you'll take ownership and drive real change. Constantly grow as you work hard for a mission that matters at a company where you matter.Your ImpactAs a senior member of the mesh & opportunistic networking team, you will own the fpga realization of the digital signal processing that powers our software-defined radio. You will take wireless communication algorithms from concept through behavioral modeling in matlab/simulink, into synthesizable rtl, and onto silicon — meeting aggressive timing, resource, and power targets on a zynq ultrascale+ mpsoc. You will apply deep expertise in dsp, digital communications, and fpga design to deliver a robust, high-performance ofdm modem, and you will collaborate closely with firmware, systems, rf, and product engineering to bring the full radio together. You will mentor junior engineers, raise the technical bar for our model-based design and verification practices, and continue to grow your own technical leadership. Join a passionate engineering team dedicated to overcoming complex challenges, and help deliver technologies that positively impact law enforcement, public safety, and their surrounding communities.Location - this role is based out of our boston or scottsdale offices and follows a hybrid schedule. We rely on in-person collaboration and ask that team members work onsite tuesdays through fridays, with the flexibility to work remotely on mondays, unless there is an approved workplace accommodation. We believe that connection fuels innovation, and our in-office culture is designed to foster meaningful teamwork, mentorship, and shared success.What You'll DoResearch, model, and implement industry-leading sdr and digital communications algorithms — ofdm modulation/demodulation, fft/ifft, channel estimation and equalization, synchronization, mimo, and forward error correction (ldpc) — for products in our mesh and connected-device portfolioDevelop floating- and fixed-point behavioral reference models in matlab/simulink, make quantization and architecture trade-offs, and validate algorithm performance against link-budget and ber/per requirementsGenerate and integrate rtl from simulink using hdl coder, and author hand-written vhdl/verilog where custom or performance-critical logic is requiredImplement designs in vivado through the full flow — synthesis, place-and-route, and timing closure — authoring and refining xdc timing and physical constraints to meet timing on high-utilization, multi-clock designsArchitect and implement on-chip interfaces and data movement: axi4 / axi4-stream, dma, register interfaces, fifos, and robust clock-domain-crossing (cdc) logicBuild and maintain rigorous verification: simulink/hdl co-simulation, bit-true comparison against the reference model, rtl testbenches, and automated regression suitesIntegrate the modem with the rf transceiver front end (e.g., adrv9001) and with the arm application cores, partitioning functionality across the heterogeneous socCollaborate with electrical engineering on concerns that span the fpga/rf boundary — power and thermal budgets, generation of test and characterization waveforms, and digital pre-distortion (dpd) for power amplifier linearizationBring up, characterize, and debug the radio on hardware using oscilloscopes, logic/protocol analyzers, spectrum and vector signal analyzers, and on-chip debug (ila/vio)Collaborate with firmware engineering to define and debug the hardware/software interface, register maps, and data pipelinesEvaluate and document design outcomes, timing/resource reports, and verification results, and present findings to the design team for review and further actionOptimize performance, area, and power through micro-architecture refinement, pipelining, and resource sharing, guided by simulation and hardware measurementDevelop and maintain design documentation, interface control documents, and release artifacts needed for product integrationMentor junior engineers and contribute to team knowledge sharing and best practices in model-based design and fpga developmentWhat You'll BringBachelor's degree in electrical engineering, computer engineering, or a similar engineering discipline6+ years of industry fpga/rtl design experience taking digital logic from architecture through synthesis, timing closure, and hardware bring-upHighly proficient in rtl design with vhdl and/or verilog/systemverilog, including synthesizable coding practices and design for testabilityStrong hands-on proficiency with the xilinx/amd vivado toolchain — synthesis, implementation, timing constraints (xdc), and timing closure on complex, high-utilization designsDemonstrated experience with matlab and simulink for algorithm modeling, and with model-based design workflowsSolid foundation in digital signal processing and digital communications: sampling, filtering, ffts, modulation/demodulation, and an understanding of wireless link fundamentalsExperience with fixed-point arithmetic, quantization analysis, and the trade-offs between numerical precision, area, and performanceProficient with on-chip interconnect and interfaces — axi4/axi4-stream, dma, memory interfaces — and with clock-domain-crossing designStrong rtl verification skills: testbench development, hdl simulation, and verifying rtl against a golden/reference modelStrong hands-on proficiency with fpga and system bring-up and debug using laboratory tools: oscilloscope, logic/protocol analyzers, spectrum/signal analyzers, and integrated logic analyzers (ila/vio)Proficient with modern ai-assisted development tools and coding assistants (e.g., claude code, cursor, github copilot), and able to apply them effectively and responsibly to accelerate design, verification, scripting, documentation, and debugIndependent contributor capable of developing complex designs within cross-functional and geographically diverse engineering teamsStrong proficiency in documentation, analysis, and presentation tools, including word, excel, and powerpointPreferred QualificationsMaster's or phd in electrical engineering, communications, or signal processingProduction experience with hdl coder (or equivalent high-level synthesis / model-to-rtl) workflows, including code generation, optimization, and verification of generated rtlHands-on experience implementing ofdm modems and/or channel coding (ldpc, turbo, convolutional/viterbi), mimo, channel estimation, and synchronization in hardwareExperience designing on zynq / zynq ultrascale+ mpsoc or other heterogeneous soc/fpga platforms, including hardware/software partitioning with embedded processorsExperience integrating wideband rf transceivers (e.g., analog devices adrv9001/adrv9002) or other sdr front ends, and implementing or supporting rf impairment correction such as digital pre-distortion (dpd)Familiarity with software-defined radio platforms and frameworks (e.g., gnu radio) and over-the-air testingExperience with version control (git) and ci for hdl/model-based designExperience applying ai coding assistants to fpga/hdl workflows — rtl generation and review, testbench creation, constraint and timing analysis, matlab/simulink and tcl scripting, and design documentation — with sound judgment about where generated output must be verifiedBenefits That Benefit YouCompetitive salary and 401k with employer matchDiscretionary paid time offPaid parental leave for allMedical, dental, vision plansFitness programsEmotional & mental wellness supportLearning & development programsAnd yes, we have snacks in our officesDon't meet every single requirement? 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