Staff Applications Engineer

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

Working directly with customers does not intimidate you. You can walk into a design team's environment, assess their RTL, their coverage gaps, and their tool setup, and walk out with a concrete plan that makes our products work for them, not against them. You do not sell vaporware. You diagnose real bottlenecks, whether it is a poorly constrained environment, a design that is blowing up state space, or a team that does not yet know how to write properties that matter.

You are technical enough to debug why a product run is stuck and pragmatic enough to know when to pivot the approach. You can explain a bounded proof failure to a design lead in two sentences and then turn around and file a detailed enhancement request with R&D. At Synopsys, you will work with customers who are building the chips that power everything, and what you help them verify today ships in products millions of people use tomorrow.

What You'll Be Doing

• Lead formal verification deployments with customers, assessing their design environments, verification gaps, and RTL complexity to recommend methodologies that actually fit their workflow
• Diagnose root causes of formal tool performance issues, whether it is state space explosion, over-constrained environments, or poorly scoped properties, and optimize formal testbenches and abstraction strategies to get results
• Identify which design blocks and verification scenarios are good candidates for formal property checking, sequential equivalence checking, connectivity checking, or formal coverage analysis
• Develop and deliver technical training on new formal features and product updates, translating release notes into practical guidance that helps customers adopt capabilities faster
• Work directly with Synopsys R&D and product engineering teams to communicate customer priorities, tool limitations, and feature requests that shape product roadmaps
• Support customers through complex formal runs, including data path logic verification, math function checks, and assertion-based verification integration
• Build reusable formal verification flows and best practices that scale across customer engagements and design types

The Impact You Will Have

• Enable customers to catch critical design bugs earlier in the verification cycle, reducing costly re-spins and time-to-market delays
• Drive adoption of formal verification across customer organizations, turning skeptical design teams into confident users who rely on formal as part of their standard methodology
• Influence Synopsys product direction by surfacing real customer pain points and use cases that R&D would not see otherwise
• Reduce formal runtime bottlenecks and false negatives, making tools faster and more reliable for production verification environments
• Build customer trust and long-term relationships by solving hard technical problems that other vendors could not crack
• Expand the footprint of Synopsys formal solutions within accounts, proving value on one block and scaling to full SoC verification programs
• Contribute to the formal verification community inside Synopsys by documenting what works, what does not, and why, so the next engineer does not start from zero

What You'll Need

• Bachelor's or Master's degree in Electrical Engineering or Computer Engineering from an accredited institution
• 5-7 years of hands-on experience in RTL design or verification, deploying advanced verification methodologies in production environments
• Deep understanding of formal verification applications including formal property checking, sequential equivalence checking, formal coverage analysis, and connectivity checking
• Strong grasp of hardware design languages like Verilog or VHDL and the ability to read and reason about micro-architecture and RTL implementations
• Proficiency in Unix/Linux environments with solid scripting skills in Tcl , Perl, Python, and shell scripting (bash, csh ) for automation and flow development
• Experience with assertion-based verification is strongly preferred, prior hands-on use of formal verification tools is a significant plus
• Exposure to verification consulting or managing verification responsibility for complex hardware designs is desirable

Who You Are

• You can walk into a customer meeting, listen to a verification challenge, and sketch out a formal approach on a whiteboard that makes sense to both the verification lead and the design architect
• You are comfortable working autonomously, you do not wait for someone to tell you what to investigate next when a formal run fails or a customer is stuck
• You know how to prioritize, when a customer has five problems, you can figure out which two actually matter and which three are noise
• You have strong written and verbal communication skills, you can write a clear bug report, deliver a training session, and explain a bounded proof result without losing your audience
• You push back when a proposed formal methodology does not fit the design or the timeline, you care more about what works than what sounds impressive
• You are curious about why things break, whether it is a tool, a testbench, or a design assumption, and you do not stop until you understand the root cause

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.