Senior Design Verification Lead, SoC Power Chips (Hybrid)
Powerlattice Technologies Inc
Powerlattice Technologies Inc seeks a Design Verification Lead to spearhead verification of complex SoCs/IPs, building scalable SystemVerilog environments and reusable test infrastructure. The role collaborates with RTL, analog, architecture, and silicon validation teams to identify and resolve design issues. The candidate will drive coverage closure, develop assertions and functional checkers, and lead a team of verification engineers in a hybrid setup across Vancouver, WA and Chandler, AZ. #J-18808-Ljbffr Powerlattice Technologies Inc
Vacancy posted 2 days ago
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