Senior FPGA RTL Design Engineer for Wireless Prototypes
ALTEN
ALTEN is looking for a PGA RTL Design Engineer in California, MO to design and develop hardware algorithms for advanced wireless communications. The ideal candidate will have 5+ years of experience in FPGA or ASIC design and be proficient in Verilog and System Verilog. The role involves debugging complex FPGA designs and developing solutions for high-speed interfaces such as DDR4 and PCIe. Join our innovative team to contribute to cutting-edge wireless technologies! #J-18808-Ljbffr ALTEN
Vacancy posted 9 hours ago
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