Design Verification Engineer

We are currently partnered with a leading Semiconductor Designer and Manufacturer based across the US, who are looking for an experienced Verification Engineer to join their team. Job Summary Designing and building verification environments using System-Verilog and Universal Verification Methodology (UVM) for integrated circuits with embedded CPUs and analog mixed-signal interfaces. Developing test plans and coverage metrics from specifications, and writing block- and chip-level tests. Automating the creation of verification environments, tests generation, and debugging using PERL/Python scripts. Skills required Knowledge and experience within the Semiconductor industry. 3+ years of experience with Verification. Experience with C Programming. Strong knowledge of VHDL, Verilog and / or UVM #J-18808-Ljbffr