Senior Mask Layout Design Engineer
$132k - $207kNvidia
Are you interested in joining our Dynamic team? If yes, We are looking for a Senior Mask Layout Design Engineer – someone who is excited to join a growing group of diverse individuals responsible for handling high-speed mixed-signal circuit designs!NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 fueled the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to tackle, that only we can pursue, and that matter to the world. This is our life’s work, to amplify human creativity and intelligence.What you'll be doing:Perform physical layout for mixed-signal functions like PLL's, high speed I/O circuits, general I/O's, ESD structures designs in innovative sub-micron CMOS technologies using Cadence toolsYou'll work with ASIC and mixed-signal engineers to customize designs for integration in VLSI products and Job duties will include floor planning, custom layout and verifying against design rules and schematics.What we need to see:Hold a BSEE or equivalent experience. MSEE is a plus.8+ years of relevant mask design / layout experienceTape-out experience with FinFET technology is required. Experience with TSMC N5/N4/N3 is preferred.Experience with high-speed SerDes/RF layout design is helpful and Experience with top level integration would be excellent to have.Deep understanding of analog circuit layout concepts in submicron CMOS technologiesValidated experience with Cadence custom circuit design tools - particularly virtuosoExperience running and debugging DRC and LVS with verification tools such as ICV/CalibreAbility to work optimally in a team, good interpersonal skills and positive energy.Proficiency in scripting languages like perl, python, skill etc. is a plusKnowledge of DRC and LVS checking flows, ability to customize DRC and LVS decksYour base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 132,000 USD - 207,000 USD for Level 4, and 148,000 USD - 235,750 USD for Level 5.You will also be eligible for equity and benefits.Applications for this job will be accepted at least until October 10, 2026.This posting is for an existing vacancy. NVIDIA uses AI tools in its recruiting processes.NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.SummaryLocation: US, CA, Santa Clara; US, TX, AustinType: Full time
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...providing a unique combination of design, development, and fabrication... ...of Role:As an MTS Product Engineer / Product Management for Universal... ...goals for Tapeout and Mask operations, specifically Product... ...Transfers: Handle huge GDSII or OASIS layout files smoothly Strong...SuggestedFull timeLocal area$105.1k - $231.1k
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We are now looking for a Senior Physical Design Engineer. NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing....SeniorFull time$168k - $264.5k
...to do their best work. Come join the team and see how you can make a lasting impact on the world.We are looking for a physical design engineer to be a part of NVIDIA’s physical design (PD) methodology team driving innovation in PD across all of NVIDIA's products - Datacenter...SeniorFull timeRemote work$168k - $264.5k
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Senior IP Design EngineerCategoryChip DesignLocationAustin, TXExperienceMore than 4 Years Work Expe.EducationMaster's DegreeJob DescriptionMediaTek... ...products, IoT devices, and more. We combine deep engineering expertise with a collaborative, fast-paced work environment...SeniorTemporary workWork experience placementWork from home- ...across every market segment of chip design, including artificial intelligence,... ...About the RoleSiFive is looking for a Senior Design Verification Engineer to drive verification of high-... ...arithmetic, vector memory operations, masking behavior, configuration-dependent execution...SeniorFull time
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...and many other applications. As part of our team, you will help design the next generation of high-performance microprocessors. We are... ...to deliver world-class products.As a CPU RTL Logic Design Engineer your responsibilities will include but are not limited to:• Collaborates...SeniorFull timeWork experience placementInternshipLocal areaImmediate startShift work$128.6k - $217.2k
Senior Physical Design EngineerCategoryChip DesignLocationAustin, TXExperienceMore than 8 Years Work Expe.EducationMaster's DegreeJob DescriptionMediaTek... ....About the RoleWe are seeking a Senior Physical Design Engineer to drive Advanced Place & Route (APR) and physical...SeniorTemporary workWork at officeWork from home- ...Wipro Limited in Austin, Texas is seeking a Physical Design Engineer with strong PnR, PPA optimization, and timing convergence to drive block-level design from netlist to GDSII. You will perform floorplanning, CTS, routing, and timing closure across advanced nodes, collaborating...Senior
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...software that bring intelligence wherever it's needed and help shape the next generation of computing. We are looking for a Senior Design Engineer to design, integrate, and sign off RTL for blocks across our power-efficient SoC: the compute fabric's on-chip interconnect...SeniorNight shift- ...Intel Corporation in Austin, TX seeks a CPU Logic Design Engineer to drive RTL coding, verification, and microarchitecture collaboration for high-performance CPUs. You will develop RTL in SystemVerilog, optimize logic for power, performance and area, and ensure design...Senior
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...Partner in Texas | Delivering the Engineers Others Can’t Find | Proud Co-... ...Engineer who enjoys owning designs end‑to‑end and working... ...fundamentals Schematic capture, PCB layout oversight, simulation, and... ...in-person collaboration Seniority level Mid-Senior level Employment...SeniorPermanent employmentFull time- ...Qualcomm Technologies, Inc. is seeking highly motivated Physical Design Engineers across multiple levels for its ASIC implementation team, including floorplanning, PnR, CTS, timing closure, and power optimization. You will collaborate with architecture, RTL, DFT, and...Senior
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