DFT Design Engineer, AWS Machine Learning Acceleration at Annapurna Labs (U.S.) Inc. Austin, TX

As a member of the Silicon Optimization Engineering Team you’ll be responsible for the design and optimization of hardware in our data centers. You’ll provide leadership in the application of new technologies to large scale server deployments in a continuous effort to deliver a world‑class customer experience. Responsibilities Develop, implement and verify state‑of‑the‑art Design for Test (DFT) architectures. Work with block designers to integrate DFT implementations. Work with physical design team to setup and implement DFT insertion flow. Develop high coverage and cost effective DFT methodologies. Perform RTL coding and verification. Participate in silicon debug and write scripts to effectively handle ATE related data. Communicate and work with team members across multiple disciplines. Qualifications BS degree in EE, CE, or CS. 3+ years of practical DFT experience with large processor and/or SoC designs. Knowledge about industry standard tools and practices in DFT, including ATPG, JTAG, MBIST and trade‑offs between test quality and test time. Experience with automation script development. #J-18808-Ljbffr Itlearn360