Staff R&D Engineer, Accelerated Verification

Overview Synopsys software engineers are key enablers in the world of Electronic Design Automation (EDA), developing and maintaining software used in chip design, verification, and manufacturing. In this role, you will develop high-performance simulation solutions utilizing GPU acceleration and parallel programming to tackle complex EDA challenges. You Are A passionate engineer specializing in simulation and verification, you excel at utilizing high-performance computing to solve complex problems. With expertise in HDL (System Verilog/VHDL), C++, and parallel models, you thrive on innovation and collaborate effectively across teams to deliver scalable solutions. What You’ll Be Doing Designing/Optimizing accelerated verification tools using massive parallelism and GPU technologies. Implementing and troubleshooting advanced graph algorithms to manage complex hardware designs. Developing GPU kernels (CUDA/HIP/DPC++) to reduce simulation runtimes. Leveraging multi-threaded programming (OpenMP/TBB) to maximize throughput. Debugging functionality and performance of compiler enhancements and optimizations. The Impact You Will Have Accelerating customer chip development cycles and enabling next-generation silicon design. Driving innovation in GPU-powered algorithms. Empowering engineering teams to achieve faster RTL sign-off. What You’ll Need Proficiency in C/C++ and performance profiling. Knowledge of GPU computing (CUDA/HIP/DPC++) and parallel memory models. Experience with multi-threaded programming (OpenMP, TBB). Knowledge in HDL (SystemVerilog/VHDL) and compiler design. AI-First Mindset: Proficiency in using modern AI‑assisted coding tools like Cursor or Claude Code to accelerate development cycles and maintain high code quality. Growth Mindset: We welcome candidates with HPC and algorithm expertise who have an interest in mastering the hardware verification domain. Desirable Skills Experience implementing high-performance graph algorithms on GPU and multicore architectures. Familiarity with distributed computing frameworks and memory-efficient data structures. Education & Experience BS in CS/EE or related field with 5+ years of experience. MS in CS/EE or related field with 3+ years of experience; advanced coursework or project work in HPC/Compilers is highly valued. PhD in CS/EE with 0-1 years of experience with focus in HPC/GPU computing. Relevant doctoral research and peer-reviewed publications in Parallel computing or EDA will be considered toward this requirement. #J-18808-Ljbffr