Collateral Design and DFM Engineer

Job Details: Job Description: About MDCE Manufacturing Development and Customer Engineering (MDCE) is Intel's newest organization within Intel Foundry Technology Manufacturing (FTM). We bridge the critical gap between Technology Development (TD) and High-Volume Manufacturing (HVM), advancing technology nodes from initial product qualification to high-yield production across multiple products while enhancing technologies for our foundry customers. MDCE is also chartered to develop new technologies on mature node infrastructure to bring new solutions to new customers at reliable yield and performance and low cost, and this is where you are going to play a role. Position Overview As a Collateral - Design and DFM Lead Engineer you will be at the heart of HVM and ramp of leading-edge advance logic technologies chartered with inventing and enhancing DFM methodologies for improving performance, yield and ramp across a diverse product portfolio. Key Responsibilities Lead cross functional teams across process integration/ device/ yield/ design/OPC/RET/DR and DTP/CAD teams to define and enhance Design for Manufacturability rules for enhanced yield /performance and faster ramp on advanced logic technologies Enhance and feed silicon learning / sighting of yield issues for design teams to update layout /DTCO methodologies, flows to capture yield issues early in the design process Work and refine yield tools/flows inside foundry and help in inline yield detection and optimization Define/Refine DFM methodologies by understanding silicon process flows and predicting and developing rules for avoiding layout and design marginalities by working with cross functional teams Ideal Candidate Excellent communication and collaboration skills with ability to interface effectively with design teams, process engineers, and external customers from diverse industry segments Qualifications Master or Ph.D. degree in Electrical Engineering, Physics, or related field with 10+ years of experience in DTCO and/or DFM within semiconductor foundry or advanced technology development environment Strong understanding of DTCO skills including understanding of SRAM, Standard cells, Process Integration, Yield, and Device. Experience in leading cross functional group in defining derivative architectures including Design rules, transistors and interconnects Experience in scribe line layout design and process monitoring structure development Proven track record in foundry environment developing and implementing DFM solutions for varied customer requirements across multiple market segments Preferred Qualifications Coding/Scripting knowledge beneficial Ability to switch between multiple projects and ability to prioritize Required exposure to foundry ecosystem with understanding of customer design flows and manufacturing constraints across various application domains Hands‑on experience in advanced node test chip design and scribe line optimization for 3nm-16nm FinFETs and sub 3nm GAA FETs, Backside power delivery Understanding of Physical Design flows for Yield Analysis, DRC, and verification flows Proficiency in design rule development, validation, and waiver management processes Job Type Experienced Hire Shift Shift 1 (United States of America) Primary Location US, California, Santa Clara Additional Locations US, Arizona, Phoenix, US, Oregon, Hillsboro Business Group Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments. Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, and assembly/test packages the compute devices to improve the lives of every person on Earth. EEO Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel. Annual Salary Range $190,650.00-269,150.00 USD Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. Additional Information Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter. Intel’s official careers website. Find your next job and take on projects that shape tomorrow’s technology. #J-18808-Ljbffr Intel Corporation