Senior FPGA Engineer with Active Secret Clearance

Would you be interested in pursuing the following Senior FPGA Engineer position Fortune 500 Aerospace/Defense Company , Collins Aerospace in Cedar Rapids, IA.

This would be a 12-Months Contract. Potential to get extended.

US Citizenship and an Active Secret Clearance is required for this position.

Please send me a word copy of your resume and your contact information if you are interested in below mentioned opportunity.

Senior FPGA Engineer Cedar Rapids, IA. Onsite only
Schedule: 1 st Shift

Pay Rate: Open

Collins Aerospace is seeking a highly skilled and innovative Senior FPGA Engineering Contractor to work with our Applied Research and Technology (ART) Microelectronics Technology team. Your work will contribute to the development of cutting-edge defense solutions across Mission Systems, leveraging your expertise in the design, implementation, verification, and integration of a wide variety of high-performance digital FPGAs.

What You Will Do

Adhere to all applicable Collins Engineering Development and Quality processes, procedures, instructions and guidelines.

Participate in Agile team meetings and planning activities, as required to support programs covered by this work plan.

Requirements, design and verification of FPGA solutions

Integration of developed FPGA on target hardware units

Supporting peer reviews and certification analysis activities

Peer reviewing FPGA development artifacts

Management of change request and task assignments through Jira

Qualifications You Must Have

Typically requires a degree in Science, Technology, Engineering or Mathematics (STEM) and minimum 5 years prior relevant experience or an Advanced Degree in a related field and minimum 3 years of experience.

An active U.S. government issued Final Secret Security Clearance is required

A minimum of 3 years professional experience in FPGA development, ASIC front end, or related areas

Proficient in VHDL/Verilog for FPGA/ASIC design and implementation.

Experience in digital circuit architecture, design, resource tradeoffs, timing analysis, and timing closure

Familiarity with FPGA platforms such as AMD/Xilinx, Altera, Microchip, or others, and associated toolchains (e.g., Vivado, Quartus, Libero).

Strong debugging and troubleshooting skills for FPGA/ASIC systems.

Proficiency with revision control concepts and tools (e.g., Git, Subversion)

Qualifications We Prefer

Excellent communication and teamwork skills with the ability to work in a collaborative environment.

Experience with high-speed digital interfaces and protocols (e.g., DDR, PCIe, Ethernet).

Familiarity with best-practice chip-level verification techniques and languages (e.g., constrained random, functional coverage, System Verilog)

Experience in ASIC / FPGA lab validation using advanced laboratory equipment

Experience with Unix, scripting, C/C++, and/or Perl.

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