Senior ASIC Verification Engineer - Pre-Silicon, Emulation & Formal

Palo Alto Networks in California seeks a Design Verification engineer for the ASIC team to ensure next-generation firewall devices meet high standards of features, performance, and reliability. You will define verification methodologies, architect test benches, write tests, and debug across simulation, emulation, formal verification, and silicon validation. Office-based with four days in the office per week.