Physical Design Engineer- Foundry Services

Job Description The Physical Design Engineer is responsible for transforming design concepts into manufacturable solutions for Intel’s Si Interposers and Bridge designs. The role ensures high-performance, power efficiency, and area optimization while advancing industry-leading methodologies and design flows. Key Responsibilities Implement physical design for Si Interposer designs, progressing from floor‑planning to a manufacturing‑ready database. Execute all aspects of the physical design flow: placement, routing, floor‑planning, routing, and physical design verification. Conduct signal integrity, power, and reliability analyses to guarantee design integrity. Perform verification and sign‑off, including formal equivalence verification, reliability verification, layout verification, electrical rule checking, and structural design checking. Analyze verification results, recommend fixes for violations, and implement corrections. Optimize designs for product‑level parameters such as signal integrity, power, reliability, density, and area. Use industry‑standard EDA tools for physical design processes, including placement, routing, and analysis. Design and manage multiple power domains, static and dynamic power integrity, and generate reports. Develop and automate physical design methodologies and flows to improve efficiency and scalability. Collaborate with cross‑functional teams to enable seamless integration of physical design across multiple projects. Drive enhancements in physical design methodologies and automation. Demonstrate excellent communication and collaboration skills within cross‑functional teams. Show passion for solving complex design challenges and contributing to innovative solutions. Minimum Qualifications US Citizenship. Ability to obtain and maintain a US Government TS/SCI Security Clearance with Polygraph. Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field with 4+ years of experience, or a Master’s degree with 3+ years of experience. Experience with EDA tools for custom physical design and Auto‑place‑n‑route (Virtuoso, Innovus, ICC, ICC2/Fusion, ICValidator, Calibre, UPF, RTL, SPICE, OASIS, ODB++). Experience with at least two of the following physical design areas: floor‑planning, routing optimization/shielding, signal integrity analysis, multi‑power‑domain power delivery design/analysis, or reliability verification. Full chip physical design completion and verification for tape‑in/tape‑out projects. Preferred Qualifications Experience optimizing designs for signal integrity and power integrity. Experience in chip‑level design and tape‑in assembly for advanced technology nodes. Job Information Job Type: Experienced Hire Shift: Shift 1 (United States) Primary Location: US, Arizona, Phoenix Work Model: On‑site presence required Salary Annual Salary Range for US positions: $122,440.00 – $232,190.00 USD. Individual pay is determined by location and experience. Benefits Intel offers a competitive compensation package that includes competitive pay, stock bonuses, and benefit programs such as health, retirement, and vacation. EEO Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. #J-18808-Ljbffr