Senior Characterization Engineer (Santa Clara)

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world.A Phase-Locked Loop (PLL) Characterization Engineer tests, analyzes, and validates PLL circuits after silicon fabrication. They ensure the circuits meet specifications for frequency range, jitter, lock time, and energy efficiency.What you'll be doing:ATE based Testing & Validation: Perform hands-on, post-silicon characterization of high-speed IOs, single-ended and differential, PLLs and related IP (VCOs, charge pumps, dividers).Performance Metrics Optimization: Characterize and optimize performance metrics, including TX eye openings, RX jitter tolerance and sensitivity, PLL phase noise, jitter (RMS/peak-to-peak), lock time, frequency range, power supply rejection ratio (PSRR), and power consumption.Develop ATE programs using the Advantest 93000 platform to automate measurements. design PCB, Operate bench equipment such as waveform analyzers and frequency analyzers when necessary. Analyze large datasets and communicate important findings to the PLL development team.Work with DFT to ensure accurate test modes are implemented in the chip development phase and help drive ATE vector generation.Debug & Root Cause Analysis: Identify and fix silicon bugs, PVT (Process, Voltage, Temperature) marginalities, and noise coupling issues.Correlation: Correlate ATE measurements with simulation results and bench test resultsDocumentation: Generate comprehensive characterization reports, test plans, and documentation for design validation teams and production teams.What we need to see:Bachelor's degree in EE or equivalent experience.12+ years of related experience.Technical Knowledge: Deep understanding of PLL architectures (Analog, Digital, Fractional-N, LC, Ring VCOs), feedback loop dynamics, and frequency synthesis. Experience in high-speed IO testing, test hardware design and signal integrity.Lab Equipment Proficiency: Experience with Advantest 9300 platform, high-speed oscilloscopes, spectrum analyzers, and vector network analyzers.Automation/Scripting: Strong proficiency in Java and C++ to automate test equipment.Experience in analog/mixed-signal validation.Collaboration: Ability to work with design, systems, and product engineering teams to drive silicon from bring-up to mass production.With competitive salaries and a generous benefits package, we are widely considered to be one of the technology world’s most desirable employers, and we have some of the most forward-thinking and hardworking people in the world working for us. Due to outstanding growth, our best-in-class teams are rapidly growing so if you're creative and autonomous with a real passion for technology, we want to hear from you.Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 184,000 USD - 287,500 USD.You will also be eligible for equity and benefits.Applications for this job will be accepted at least until February 23, 2026.This posting is for an existing vacancy. NVIDIA uses AI tools in its recruiting processes.NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.SummaryLocation: US, CA, Santa ClaraType: Full time