Design Verification Engineer

Design Verification Engineer

Location: Bay Area (Day1 onsite preferable)

Client: Google, Facebook, Cisco, Intel Mandatory: UVM minimum 3 years of experience also share a write up along with the submission

Must be proficient with:

• Building a test bench for a block using System Verilog and UVM
• Writing random tests, directed tests, error tests & performance tests for a block of Verilog and UVM.
• Developing, maintaining and supporting of the UVM verification environment.
• Debugging tests with design engineers to deliver functionally correct design blocks
• Writing & analyzing functional coverage, assertions
• Generating and analyzing code coverage & writing waivers.

Thanks & Regards,

Akhil Reddy Vontela

Software Technology Inc

100 Overlook Center, Suite 200 Princeton, NJ 08540.

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